{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:45:29Z","timestamp":1776955529821,"version":"3.51.4"},"reference-count":71,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9474024","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"page":"517-522","source":"Crossref","is-referenced-by-count":20,"title":["Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling"],"prefix":"10.23919","author":[{"given":"Seyed Saber","family":"Nabavi Larimi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Behzad","family":"Salami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Osman S.","family":"Unsal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adrian Cristal","family":"Kestelman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Sarbazi-Azad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref71","article-title":"Adaptive Guardband Scheduling to Improve System-Level Efficiency of the POWER7+","author":"zu","year":"2015","journal-title":"Micro"},{"key":"ref70","article-title":"Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs","author":"zou","year":"2018","journal-title":"Micro"},{"key":"ref39","article-title":"Research Problems and Opportunities in Memory Systems","author":"mutlu","year":"2015","journal-title":"SUPER"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref33","year":"2020","journal-title":"Low Power Double Data Rate 4 (LPDDR4)"},{"key":"ref32","article-title":"Fast Voltage Transients on FPGAs: Impact and Mitigation Strategies","author":"linda","year":"2019","journal-title":"FCCM"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090716"},{"key":"ref30","article-title":"Safe Limits on Voltage Reduction Efficiency in GPUs: A Direct Measurement Approach","author":"leng","year":"2015","journal-title":"Micro"},{"key":"ref37","article-title":"A Modern Primer on Processing in Memory","author":"mutlu","year":"0","journal-title":"Proc Springer"},{"key":"ref36","article-title":"Inside Solid State Drives (SSDs)","author":"micheloni","year":"0","journal-title":"Proc Springer"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCS48598.2019.9188158"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.50"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/CAHPC.2018.8645906"},{"key":"ref62","year":"2020","journal-title":"Virtex UltraScale+ HBM VCU128-ESI FPGA evaluation kit Xilinx Inc"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.56"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815973"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056030"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"ref65","article-title":"Virtex Ultrascale+ HBM FPGA: a Revolutionary Increase in Memory Performance (WP485)","author":"wissolik","year":"2019","journal-title":"Xilinx Inc"},{"key":"ref66","year":"0","journal-title":"Xilinx Virtex UltraScale+ HBM"},{"key":"ref29","article-title":"GPUWattch: Enabling Energy Optimizations in GPG-PUs","author":"leng","year":"2013","journal-title":"ISCA"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2017.117"},{"key":"ref68","article-title":"SRAM Voltage Scaling for Energy-Efficient Convolutional Neural Networks","author":"yang","year":"2017","journal-title":"ISQED"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465918"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485948"},{"key":"ref1","first-page":"461","article-title":"Energy-efficient cache design using variable-strength error-correcting codes","author":"alameldeen","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref20","year":"2020","journal-title":"High-bandwidth Memory (HBM) DRAM"},{"key":"ref22","article-title":"Focus: Querying Large Video Datasets with Low Latency and Low Cost","author":"hsieh","year":"2018","journal-title":"OSDI"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2018.021651341"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref23","article-title":"EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference using Approximate DRAM","author":"koppula","year":"2019","journal-title":"Micro"},{"key":"ref26","article-title":"HBM: Memory Solution for Bandwidth-Hungry Processors","author":"lee","year":"2014","journal-title":"HCS"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798233"},{"key":"ref51","article-title":"Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling","author":"reddi","year":"2010","journal-title":"Micro"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.28"},{"key":"ref58","article-title":"Fault Characterization through FPGA Undervolting: Fault Characterization and Mitigation","author":"salami","year":"2018","journal-title":"FPL"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.2019.8671543"},{"key":"ref56","article-title":"Comprehensive Evaluation of Supply Voltage Under-scaling in FPGA On-Chip Memories","author":"salami","year":"2018","journal-title":"Micro"},{"key":"ref55","article-title":"AxleDB: A Novel Programmable Query Processing Platform on FPGA","author":"salami","year":"2017","journal-title":"MICPRO"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/DSN48063.2020.00032"},{"key":"ref53","author":"salami","year":"2018","journal-title":"Aggressive Undervolting of FPGAs Power and Reliability Trade-offs"},{"key":"ref52","year":"2020","journal-title":"RLDRAM Memory Micron Technology Inc"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.61"},{"key":"ref11","article-title":"Calculating Memory Power for DDR4 SDRAM","year":"2017","journal-title":"Micron Technology Inc"},{"key":"ref40","article-title":"Power and Energy Reduction of Racetrack-based Caches by Exploiting Shared Shift Operations","author":"nabavi","year":"2016","journal-title":"VLSI-SoC"},{"key":"ref12","article-title":"Understanding Reduced-voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms","author":"chang","year":"2017","journal-title":"POMACS"},{"key":"ref13","article-title":"Memory Power Management via Dynamic Volt-agelFrequency Scaling","author":"david","year":"2011","journal-title":"ICAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950392"},{"key":"ref15","doi-asserted-by":"crossref","DOI":"10.1145\/3376930.3376989","article-title":"Demystifying Complex Workload-DRAM Interactions: An Experimental Study","author":"ghose","year":"2019","journal-title":"SIGMETRICS"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3219617.3219661"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2019.8854386"},{"key":"ref18","year":"2018","journal-title":"Graphics Double Data Rate 6 (GDDR6) SGDRAM Standard"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00029"},{"key":"ref4","article-title":"Error Analysis and Retention-Aware Error Management for NAND Flash Memory","author":"cai","year":"2013","journal-title":"Intel Technology Journal (ITJ)"},{"key":"ref3","article-title":"Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities","author":"bertran","year":"2014","journal-title":"Micro"},{"key":"ref6","article-title":"Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis","author":"cai","year":"2012","journal-title":"DATE"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2713127"},{"key":"ref8","article-title":"Reliability Issues in Flash-Memory-Based Solid-State Drives: Experimental Analysis, Mitigation, Recovery","author":"cai","year":"0","journal-title":"Proc Springer Inside Solid State Drives (SSDs)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.49"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001165"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.266"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.2200\/S00381ED1V01Y201109CAC018"},{"key":"ref45","year":"0","journal-title":"Power Management Bus (PMBUS)"},{"key":"ref48","year":"0","journal-title":"Radeon™ Pro Vega II Graphics - AMD"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00033"},{"key":"ref41","year":"2020","journal-title":"NVIDIA A100 Tensor Core GPU Unprecedented Acceleration at Every Scale"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2018.00043"},{"key":"ref43","article-title":"Harnessing Voltage Margins for Energy-Efficiency in Multicore CPUs","author":"papadimitriou","year":"2017","journal-title":"Micro"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2021,2,1]]},"end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09474024.pdf?arnumber=9474024","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,28]],"date-time":"2022-01-28T23:02:31Z","timestamp":1643410951000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9474024\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":71,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9474024","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}