{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,9]],"date-time":"2026-03-09T15:00:33Z","timestamp":1773068433967,"version":"3.50.1"},"reference-count":18,"publisher":"IEEE","funder":[{"DOI":"10.13039\/100004358","name":"Samsung Electronics Co., Ltd.","doi-asserted-by":"publisher","award":["SRFC-TC1603-51"],"award-info":[{"award-number":["SRFC-TC1603-51"]}],"id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"Nano-Material Technology Development Program through the National Research Foundation of Korea (NRF)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100014188","name":"MSIT","doi-asserted-by":"publisher","award":["NRF2016M3A7B4910249"],"award-info":[{"award-number":["NRF2016M3A7B4910249"]}],"id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9474056","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"page":"856-861","source":"Crossref","is-referenced-by-count":10,"title":["Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs"],"prefix":"10.23919","author":[{"given":"Yulhwa","family":"Kim","sequence":"first","affiliation":[]},{"given":"Hyungjun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jihoon","family":"Park","sequence":"additional","affiliation":[]},{"given":"Hyunmyung","family":"Oh","sequence":"additional","affiliation":[]},{"given":"Jae-Joon","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778160"},{"key":"ref11","article-title":"WRPN: wide reduced-precision networks","author":"mishra","year":"2017","journal-title":"ArXiv Preprint"},{"key":"ref12","article-title":"XNOR-Net++: Improved binary neural networks","author":"bulat","year":"0","journal-title":"British Machine Vision Conference (BMVC)"},{"key":"ref13","article-title":"Bi-real net: Enhancing the performance of 1-bit cnns with improved representational capability and advanced training algorithm","author":"liu","year":"0","journal-title":"European Conference on Computer Vision (ECCV)"},{"key":"ref14","article-title":"Identity Mappings in Deep Residual Networks","author":"he","year":"0","journal-title":"European Conference on Computer Vision (ECCV)"},{"key":"ref15","article-title":"Batch normalization: Accelerating deep network training by reducing internal covariate shift","author":"loffe","year":"0","journal-title":"International Conference on Machine Learning (ICML)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287718"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.29007\/22vr","article-title":"Precision highway for ultra low-precision quantization","author":"park","year":"2018","journal-title":"ArXiv Preprint"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268337"},{"key":"ref4","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or -1","author":"courbariaux","year":"2016","journal-title":"ArXiv Preprint"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2894756"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3015178"},{"key":"ref5","article-title":"XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks","author":"sun","year":"0","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE)"},{"key":"ref8","article-title":"Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators","author":"kim","year":"2018","journal-title":"ArXiv Preprint"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2943047"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2019.2934831"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2917852"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858419"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2021,2,1]]},"end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09474056.pdf?arnumber=9474056","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T20:41:05Z","timestamp":1643316065000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9474056\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":18,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9474056","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}