{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,7]],"date-time":"2025-06-07T04:50:23Z","timestamp":1749271823587,"version":"3.37.3"},"reference-count":17,"publisher":"IEEE","funder":[{"DOI":"10.13039\/501100004837","name":"Spanish Ministry of Science and Innovation","doi-asserted-by":"publisher","award":["PID2019-107255GB"],"award-info":[{"award-number":["PID2019-107255GB"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100010663","name":"European Research Council","doi-asserted-by":"publisher","award":["772773"],"award-info":[{"award-number":["772773"]}],"id":[{"id":"10.13039\/100010663","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9474078","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"page":"1162-1165","source":"Crossref","is-referenced-by-count":5,"title":["Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence"],"prefix":"10.23919","author":[{"given":"Roger","family":"Pujol","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Tabani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohamed","family":"Hassan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Civil Certification of Multi-core Processing Systems in Commercial Avionics","year":"2018","author":"radack","key":"ref10"},{"journal-title":"Document Number IMX6SLLCE","article-title":"N. Semiconductors. Chip Errata for the i.MX 6SLL","year":"2019","key":"ref11"},{"key":"ref12","article-title":"On how to identify cache coherence: Case of the NXP qoriq T4240","author":"sensfelder","year":"2020","journal-title":"ECRTS"},{"key":"ref13","article-title":"Enabling predictable, simultaneous and coherent data sharing in mixed criticality systems","author":"sritharan","year":"2019","journal-title":"RTSS"},{"journal-title":"Intel paves the road for bmw's inext autonomous cars in 2021","year":"2017","author":"suleman","key":"ref14"},{"key":"ref15","article-title":"MESI-Based Cache Coherence for Hard Real-Time Multicore Systemsgh","author":"uhrig","year":"2015","journal-title":"ARCS LNCS"},{"journal-title":"Document Number AR# 68878","article-title":"Xilinx. Zynq UltraScale+ MPSoC, APU - PMU Counter Values Might Be Inaccurate When Monitoring Certain Events","year":"2017","key":"ref16"},{"journal-title":"Xilinx Zynq UltraScale+ Device Technical Reference Manual","year":"0","key":"ref17"},{"journal-title":"E500mc Core Reference Manual","article-title":"Freescale semicondutor","year":"2014","key":"ref4"},{"key":"ref3","article-title":"Contention in multicore hardware shared resources: Understanding of the state of the art","author":"fernandez","year":"0","journal-title":"WCET Workshop"},{"key":"ref6","article-title":"Discriminative coherence: Balancing performance and latency bounds in data-sharing multi-core real-time systems","author":"hassan","year":"2020","journal-title":"ECRTS"},{"journal-title":"QorIQ T2080 Reference Manual","article-title":"Freescale semicondutor","year":"2016","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057728"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2017.13"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2009.37"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3341105.3373955"},{"key":"ref9","article-title":"On-Board Payload Data Processing requirements and technology trends","author":"notebaert","year":"0","journal-title":"OBDP Workshop - ESA\/ESTEC"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2021,2,1]]},"location":"Grenoble, France","end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09474078.pdf?arnumber=9474078","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T20:50:22Z","timestamp":1643316622000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9474078\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":17,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9474078","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}