{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T00:12:42Z","timestamp":1773792762219,"version":"3.50.1"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000266","name":"EPSRC","doi-asserted-by":"publisher","award":["EP\/N023641\/1"],"award-info":[{"award-number":["EP\/N023641\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9474117","type":"proceedings-article","created":{"date-parts":[[2021,8,10]],"date-time":"2021-08-10T20:30:23Z","timestamp":1628627423000},"page":"366-369","source":"Crossref","is-referenced-by-count":2,"title":["Synthesis of SI Circuits from Burst-Mode Specifications"],"prefix":"10.23919","author":[{"given":"Alex","family":"Chan","sequence":"first","affiliation":[{"name":"Newcastle University,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Danil","family":"Sokolov","sequence":"additional","affiliation":[{"name":"Newcastle University,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor","family":"Khomenko","sequence":"additional","affiliation":[{"name":"Newcastle University,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Lloyd","sequence":"additional","affiliation":[{"name":"Dialog Semiconductor,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Yakovlev","sequence":"additional","affiliation":[{"name":"Newcastle University,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"199","article-title":"Signal graphs: From self-timed to timed ones","author":"rosenblum","year":"0","journal-title":"Int Workshop on Timed Petri Nets"},{"key":"ref11","article-title":"Synthesis of self-timed VLSI circuits from graph-theoretic specifications","author":"chu","year":"1987","journal-title":"MIT USA"},{"key":"ref12","first-page":"315","article-title":"Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers","volume":"e80 d","author":"cortadella","year":"1997","journal-title":"IEICE Trans Information and Systems"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CSD.2004.1309112"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1994.326848"},{"key":"ref15","first-page":"451","article-title":"A novel tool for synth. by direct mapping of async. circuits from extended STG specifications","author":"mendes","year":"2018","journal-title":"vlsid"},{"key":"ref16","first-page":"225","article-title":"A tools flow for synthesis of async. control circuits from extended STG specifications","author":"delsoto","year":"2019","journal-title":"LASCAS"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/INTERCON50315.2020.9220219"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1999.761530"},{"key":"ref19","year":"0","journal-title":"Workcraft"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2019.8862081"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/5.740016"},{"key":"ref6","first-page":"204","article-title":"A theory of asynchronous circuits","author":"muller","year":"0","journal-title":"Int Symp Theory of Switching"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2017.8"},{"key":"ref8","first-page":"192","article-title":"Synthesis of asynchronous state machines using a local clock","author":"nowick","year":"1991","journal-title":"ICCD"},{"key":"ref7","author":"nowick","year":"1993","journal-title":"Automatic synthesis of burst-mode asynchronous controllers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/0471224146"},{"key":"ref1","article-title":"Principles of Async","author":"sparso","year":"2002","journal-title":"Circuit Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.743711"},{"key":"ref20","first-page":"429","article-title":"The state explosion problem","author":"valmari","year":"1996","journal-title":"Lectures on Petri Nets I Basic Models Advances in Petri Nets"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.196"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2021,2,1]]},"end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09474117.pdf?arnumber=9474117","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:22:37Z","timestamp":1773778957000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9474117\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":21,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9474117","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}