{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T23:59:15Z","timestamp":1762041555034,"version":"build-2065373602"},"reference-count":41,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9474119","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"page":"890-895","source":"Crossref","is-referenced-by-count":7,"title":["Compute-in-Memory Upside Down: A Learning Operator Co-Design Perspective for Scalability"],"prefix":"10.23919","author":[{"given":"Shamma","family":"Nasrin","sequence":"first","affiliation":[]},{"given":"Priyesh","family":"Shukla","sequence":"additional","affiliation":[]},{"given":"Shruthi","family":"Jaisimha","sequence":"additional","affiliation":[]},{"given":"Amit Ranjan","family":"Trivedi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"1303","article-title":"Stochastic variational inference","volume":"14","author":"hoffman","year":"2013","journal-title":"The Journal of Machine Learning Research"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1137\/080737770"},{"key":"ref33","first-page":"234","article-title":"14.3 a 65nm computing-in-memory-based cnn processor with 2.9-to-35.8 tops\/w system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter\/intra-macro data reuse","author":"yue","year":"0","journal-title":"2020 IEEE International Solid-State Circuits Conference-(ISSCC)"},{"key":"ref32","first-page":"244","article-title":"15.4 a 22nm 2mb reram compute-in-memory macro with 121–28tops\/w for multibit mac computing for tiny ai edge devices","author":"xue","year":"0","journal-title":"2020 IEEE International Solid-State Circuits Conference-(ISSCC)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2992886"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9180701"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1137\/080733243"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322271"},{"key":"ref35","article-title":"Mf-net: Compute-in-memory SRAM for multibit precision inference using memory-immersed data conversion and multiplication-free operators","author":"nasrin","year":"2020","journal-title":"ArXiv Preprint"},{"key":"ref34","first-page":"500","article-title":"33.2 a fully integrated analog reram based 78.4 tops\/w compute-in-memory chip with fully parallel mac computing","author":"liu","year":"0","journal-title":"2020 IEEE International Solid-State Circuits Conference-(ISSCC)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6528\/abae97"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2018.2889881"},{"key":"ref40","first-page":"1050","article-title":"Dropout as a bayesian approximation: Representing model uncertainty in deep learning","author":"gal","year":"0","journal-title":"International Conference on Machine Learning"},{"key":"ref12","first-page":"1","article-title":"Ultralow power acoustic feature-scoring using gaussian IV transistors","author":"trivedi","year":"0","journal-title":"Design Automation Conference (DAC)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-020-15378-7"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-019-12035-6"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevApplied.11.014063"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1126\/sciadv.aau5759"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECOC.2008.4729553"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.01.009"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3038908"},{"key":"ref28","first-page":"81","author":"kang","year":"0","journal-title":"A variation-tolerant dima via on-chip training"},{"journal-title":"Pcram memory cell and method of making same","year":"2006","author":"harshfield","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3319458"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/46\/9\/093001"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-018-0180-5"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9180924"},{"key":"ref5","first-page":"17","article-title":"Nvm neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning","author":"k","year":"0","journal-title":"IEEE International Electron Devices Meeting (IEDM)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2018.00210"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1038\/s41598-017-17937-3","article-title":"Insulator-metal transition in substrate-independent vo 2 thin film for phase-change devices","volume":"7","author":"taha","year":"2017","journal-title":"Scientific Reports"},{"key":"ref2","first-page":"641","volume":"577","author":"yao","year":"0","journal-title":"Fully hardware-implemented memristor convolutional neural network"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1065","DOI":"10.3390\/electronics8101065","article-title":"A spiking neural network based on the model of vo2-neuron","volume":"8","author":"belyaev","year":"2019","journal-title":"Electronics"},{"journal-title":"Memristors and Memristive Systems","year":"2013","author":"tetzlaff","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2019.2915953"},{"key":"ref22","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding","author":"han","year":"2015","journal-title":"ArXiv Preprint"},{"key":"ref21","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to+ 1 or-1","author":"courbariaux","year":"2016","journal-title":"ArXiv Preprint"},{"key":"ref24","first-page":"1","article-title":"Parallelizing SRAM arrays with customized bitcell for binary neural networks","author":"liu","year":"0","journal-title":"2018 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC) DAC"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3309551"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ICRA.2014.6907298"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2829522"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2021,2,1]]},"location":"Grenoble, France","end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09474119.pdf?arnumber=9474119","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,28]],"date-time":"2022-01-28T22:41:33Z","timestamp":1643409693000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9474119\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":41,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9474119","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}