{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,3]],"date-time":"2025-10-03T17:44:31Z","timestamp":1759513471346,"version":"3.37.3"},"reference-count":28,"publisher":"IEEE","funder":[{"DOI":"10.13039\/501100000923","name":"Australian Research Council","doi-asserted-by":"publisher","award":["DP190103743"],"award-info":[{"award-number":["DP190103743"]}],"id":[{"id":"10.13039\/501100000923","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9474214","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"page":"627-632","source":"Crossref","is-referenced-by-count":16,"title":["Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core"],"prefix":"10.23919","author":[{"given":"Nils","family":"Wistoff","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Moritz","family":"Schneider","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frank K.","family":"Gurkaynak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gernot","family":"Heiser","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/138873.138876"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1948.tb01338.x"},{"key":"ref12","first-page":"690","article-title":"A Tool for Estimating Information Leakage","author":"chothia","year":"2013","journal-title":"Computer Aided Verification"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"journal-title":"Arianespace","year":"2017","author":"zaruba","key":"ref14"},{"journal-title":"Memory subsystem for the first fully open-source RISC-V heterogeneous SoC","year":"2019","author":"r\u00f6nninger","key":"ref15"},{"journal-title":"Principled elimination of microarchitectural timing channels through operating-system enforced time protection","year":"2019","author":"ge","key":"ref16"},{"journal-title":"Timing channel benchmarking tool","year":"2015","key":"ref17"},{"journal-title":"Mastik A Micro-Architectural Side-Channel Toolkit","year":"2016","author":"yarom","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2560537"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3317550.3321431"},{"key":"ref4","first-page":"291","article-title":"POWERT channels: A novel class of covert communication exploiting power management vulnerabilities","author":"khatamifard","year":"2019","journal-title":"2019 IEEE HPCA IEEE"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715004"},{"key":"ref3","first-page":"865","article-title":"Thermal covert channels on multi-core platforms","author":"masti","year":"2015","journal-title":"Usenix Sec '15"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1007\/s13389-016-0141-6","article-title":"A survey of microarchitectural timing attacks and countermeasures on contemporary hardware","volume":"8","author":"ge","year":"2018","journal-title":"Journal of Cryptographic Engineering"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3265723.3265724"},{"key":"ref7","first-page":"1:1","article-title":"Time protection: The missing OS abstraction","author":"ge","year":"2019","journal-title":"EuroSys ‘10"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2013.35"},{"key":"ref9","article-title":"Cache missing for fun and profit","author":"percival","year":"2005","journal-title":"BSDCan"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/362375.362389"},{"journal-title":"Ariane - branch fence-t","year":"2020","author":"wistoff","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2893177"},{"journal-title":"Flushgeist Cache leaks from beyond the flush","year":"2020","author":"vila","key":"ref21"},{"key":"ref24","first-page":"280","article-title":"Partitioned cache architecture as a side-channel defence mechanism","volume":"2005","author":"page","year":"2005","journal-title":"IACR Cryptology ePrint Archive"},{"journal-title":"seL4 benchmarking applications and support library","year":"2014","author":"lyons","key":"ref23"},{"key":"ref26","first-page":"83","article-title":"A novel cache architecture with enhanced performance and security","year":"2008","journal-title":"MICRO 2008"},{"key":"ref25","first-page":"494","author":"wang","year":"2007","journal-title":"New Cache Designs for Thwarting Software Cache-based Side Channel Attacks"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2021,2,1]]},"location":"Grenoble, France","end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09474214.pdf?arnumber=9474214","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,28]],"date-time":"2022-01-28T20:49:32Z","timestamp":1643402972000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9474214\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":28,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9474214","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}