{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T14:49:06Z","timestamp":1781621346675,"version":"3.54.5"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,3,14]]},"DOI":"10.23919\/date54114.2022.9774504","type":"proceedings-article","created":{"date-parts":[[2022,5,19]],"date-time":"2022-05-19T16:35:05Z","timestamp":1652978105000},"page":"1401-1406","source":"Crossref","is-referenced-by-count":3,"title":["Triple-Skipping Near-MRAM Computing Framework for AIoT Era"],"prefix":"10.23919","author":[{"given":"Juntong","family":"Chen","sequence":"first","affiliation":[{"name":"National ASIC System Engineering Research Center, Southeast University,Nanjing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hao","family":"Cai","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Research Center, Southeast University,Nanjing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bo","family":"Liu","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Research Center, Southeast University,Nanjing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jun","family":"Yang","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Research Center, Southeast University,Nanjing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465793"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080254"},{"key":"ref13","year":"2020","journal-title":"MTJ Compact Model"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547681"},{"key":"ref15","year":"2021","journal-title":"Embedded Microprocessor Benchmark Consortium (EEMBC)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614639"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2017.2778940"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196009"},{"key":"ref4","first-page":"60","article-title":"4. 4 A 1. 3TOPS\/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1. 7 ?W Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode","volume":"64","author":"rossi","year":"0","journal-title":"2021 IEEE International Solid-State Circuits Conference-(ISSCC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474073"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287637"},{"key":"ref5","article-title":"A Survey of Quantization Methods for Efficient Neural Network Inference","volume":"abs 2103 13630","author":"gholami","year":"2021","journal-title":"CoRR"},{"key":"ref8","first-page":"189","article-title":"Per-mDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matrices","author":"deng","year":"0","journal-title":"2018 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268339"},{"key":"ref2","first-page":"100","article-title":"29. 8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU","volume":"64","author":"li","year":"0","journal-title":"2021 IEEE International Solid-State Circuits Conference-(ISSCC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2015.29"},{"key":"ref9","first-page":"224","article-title":"13. 4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42. 6GB\/s Read Bandwidth for Security-Aware Mobile Devices","author":"chang","year":"0","journal-title":"2020 IEEE International Solid-State Circuits Conference-(ISSCC)"}],"event":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Antwerp, Belgium","start":{"date-parts":[[2022,3,14]]},"end":{"date-parts":[[2022,3,23]]}},"container-title":["2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9774496\/9774497\/09774504.pdf?arnumber=9774504","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,11]],"date-time":"2022-07-11T16:06:17Z","timestamp":1657555577000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9774504\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,3,14]]},"references-count":18,"URL":"https:\/\/doi.org\/10.23919\/date54114.2022.9774504","relation":{},"subject":[],"published":{"date-parts":[[2022,3,14]]}}}