{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:54:04Z","timestamp":1730343244220,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,3,14]]},"DOI":"10.23919\/date54114.2022.9774544","type":"proceedings-article","created":{"date-parts":[[2022,5,19]],"date-time":"2022-05-19T20:35:05Z","timestamp":1652992505000},"page":"274-279","source":"Crossref","is-referenced-by-count":0,"title":["Improving Technology Mapping for And-Inverter-Cones"],"prefix":"10.23919","author":[{"given":"Martin","family":"Thummler","sequence":"first","affiliation":[{"name":"Chair for Processor Design, CfAED Technische Universit&#x00E4;t Dresden,Germany"}]},{"given":"Shubham","family":"Rai","sequence":"additional","affiliation":[{"name":"Chair for Processor Design, CfAED Technische Universit&#x00E4;t Dresden,Germany"}]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[{"name":"Chair for Processor Design, CfAED Technische Universit&#x00E4;t Dresden,Germany"}]}],"member":"263","reference":[{"key":"ref10","article-title":"A technology mapper for depth-constrained FPGA logic cells","author":"jiang","year":"2015","journal-title":"FPL"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397290"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554791"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2884646"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174256"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174272"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3092167"},{"key":"ref8","volume":"6174","author":"brayton","year":"2010","journal-title":"ABC An academic industrial-strength verification tool"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021750"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145715"}],"event":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2022,3,14]]},"location":"Antwerp, Belgium","end":{"date-parts":[[2022,3,23]]}},"container-title":["2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9774496\/9774497\/09774544.pdf?arnumber=9774544","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,11]],"date-time":"2022-07-11T20:06:05Z","timestamp":1657569965000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9774544\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,3,14]]},"references-count":13,"URL":"https:\/\/doi.org\/10.23919\/date54114.2022.9774544","relation":{},"subject":[],"published":{"date-parts":[[2022,3,14]]}}}