{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T17:11:00Z","timestamp":1773249060997,"version":"3.50.1"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100011688","name":"ECSEL Joint Undertaking","doi-asserted-by":"publisher","award":["101007273"],"award-info":[{"award-number":["101007273"]}],"id":[{"id":"10.13039\/501100011688","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,3,14]]},"DOI":"10.23919\/date54114.2022.9774571","type":"proceedings-article","created":{"date-parts":[[2022,5,19]],"date-time":"2022-05-19T20:35:05Z","timestamp":1652992505000},"page":"1413-1418","source":"Crossref","is-referenced-by-count":16,"title":["Referencing-in-Array Scheme for RRAM-based CIM Architecture"],"prefix":"10.23919","author":[{"given":"Abhairaj","family":"Singh","sequence":"first","affiliation":[{"name":"TU Delft,Computer Engineering Laboratory,The Netherlands"}]},{"given":"Rajendra","family":"Bishnoi","sequence":"additional","affiliation":[{"name":"TU Delft,Computer Engineering Laboratory,The Netherlands"}]},{"given":"Rajiv V.","family":"Joshi","sequence":"additional","affiliation":[{"name":"IBM Thomas J. Watson Research Centre,Yorktown Heights,NY,USA,10598"}]},{"given":"Said","family":"Hamdioui","sequence":"additional","affiliation":[{"name":"TU Delft,Computer Engineering Laboratory,The Netherlands"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927081"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614639"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3067385"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT49897.2020.9278288"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614642"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3149-1"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref18","article-title":"Fast boolean logic mapped on memristor crossbar","author":"xie","year":"2015","journal-title":"ICCD"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0970"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref3","article-title":"Multi state memristive tantalum oxide devices for ternary arithmetic","author":"kim","year":"2016","journal-title":"Scientific Reports"},{"key":"ref6","article-title":"Computing in memory with spin-transfer torque magnetic RAM","author":"jain","year":"2017","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2017.39"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3370748.3406572"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858415"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401226"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1002\/aisy.202000141"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702542"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722184"},{"key":"ref22","article-title":"1 T1MTJ STT-MRAM cell array design with an adaptive reference voltage generator for improving device variation tolerance","author":"koike","year":"2015","journal-title":"IMW"},{"key":"ref21","article-title":"CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors","author":"chen","year":"2019","journal-title":"Nature"},{"key":"ref24","article-title":"Novel 1T2R1T RRAM-based ternary content address-able memory for large scale pattern recognition","author":"ly","year":"2019","journal-title":"IEDM"},{"key":"ref23","article-title":"A logic resistive memory chip for embedded key storage with physical security","author":"xie","year":"2015","journal-title":"IEEE TCAS-II Express Briefs"}],"event":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Antwerp, Belgium","start":{"date-parts":[[2022,3,14]]},"end":{"date-parts":[[2022,3,23]]}},"container-title":["2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9774496\/9774497\/09774571.pdf?arnumber=9774571","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T20:49:25Z","timestamp":1658177365000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9774571\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,3,14]]},"references-count":24,"URL":"https:\/\/doi.org\/10.23919\/date54114.2022.9774571","relation":{},"subject":[],"published":{"date-parts":[[2022,3,14]]}}}