{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T16:17:51Z","timestamp":1758125871754},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,3,14]]},"DOI":"10.23919\/date54114.2022.9774743","type":"proceedings-article","created":{"date-parts":[[2022,5,19]],"date-time":"2022-05-19T16:35:05Z","timestamp":1652978105000},"page":"1377-1382","source":"Crossref","is-referenced-by-count":5,"title":["CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance"],"prefix":"10.23919","author":[{"given":"Lokesh","family":"Siddhu","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Delhi,Dept. of Comp. Sc. and Engg."}]},{"given":"Rajesh","family":"Kedia","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi,Khosla School of IT"}]},{"given":"Preeti Ranjan","family":"Panda","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi,Dept. of Comp. Sc. and Engg."}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763053"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364540"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2228267"},{"key":"ref13","article-title":"Heterogeneous HMC+DDRx memory management for performance-temperature tradeoffs","author":"hajkazemi","year":"2017","journal-title":"JETCS"},{"key":"ref14","article-title":"Leakage-aware dynamic thermal management of 3D memories","author":"siddhu","year":"2020","journal-title":"TODAES"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00032"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2642587"},{"key":"ref17","article-title":"SysScale: Exploiting multi-domain dynamic voltage and frequency scaling for energy efficient mobile processors","author":"yahya","year":"2020","journal-title":"ISCA"},{"key":"ref18","article-title":"Reducing memory interference in multicore systems via application-aware memory channel partitioning","author":"muralidhara","year":"2011","journal-title":"Micro"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2409847"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.188"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934616"},{"key":"ref6","article-title":"Temperature-aware adaptive VM allocation in heterogeneous data cen-ters","author":"kim","year":"2019","journal-title":"ISLPED"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3343030"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415682"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116510"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2752706"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430640"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0046"},{"key":"ref20","first-page":"1","article-title":"CoMeT: An integrated interval thermal simulation toolchain for 2D, 2.5D, and 3D processor-memory systems","author":"siddhu","year":"2021","journal-title":"ArXiv"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0083"},{"journal-title":"Thermal management for systems using Intel&#x00AE; Xeon&#x00AE; processors","year":"0","key":"ref21"}],"event":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2022,3,14]]},"location":"Antwerp, Belgium","end":{"date-parts":[[2022,3,23]]}},"container-title":["2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9774496\/9774497\/09774743.pdf?arnumber=9774743","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T16:49:29Z","timestamp":1658162969000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9774743\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,3,14]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date54114.2022.9774743","relation":{},"subject":[],"published":{"date-parts":[[2022,3,14]]}}}