{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:19:24Z","timestamp":1774365564869,"version":"3.50.1"},"reference-count":51,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.23919\/date56975.2023.10136923","type":"proceedings-article","created":{"date-parts":[[2023,6,2]],"date-time":"2023-06-02T19:32:57Z","timestamp":1685734377000},"page":"1-10","source":"Crossref","is-referenced-by-count":3,"title":["Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures"],"prefix":"10.23919","author":[{"given":"M.","family":"Niemier","sequence":"first","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA"}]},{"given":"X.S.","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA"}]},{"given":"L.","family":"Liu","sequence":"additional","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA"}]},{"given":"M.","family":"Sharifi","sequence":"additional","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA"}]},{"given":"Ian","family":"O\u2019Connor","sequence":"additional","affiliation":[{"name":"Ećole Centrale de Lyon,Lyon,France"}]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[{"name":"École Poly technique FÉdÉrale de Lausanne,Lausanne,Switzerland"}]},{"given":"Giovanni","family":"Ansaloni","sequence":"additional","affiliation":[{"name":"École Poly technique FÉdÉrale de Lausanne,Lausanne,Switzerland"}]},{"given":"Can","family":"Li","sequence":"additional","affiliation":[{"name":"The University of Hong Kong,Hong Kong"}]},{"given":"Asif","family":"Khan","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology,Atlanta,GA,USA"}]},{"given":"Daniel C.","family":"Ralph","sequence":"additional","affiliation":[{"name":"Cornell University,Ithaca,NY,USA"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774572"},{"key":"ref12","article-title":"Nvmexplorer: A framework for cross-stack comparisons of embedded non-volatile memories","author":"pentecost","year":"2021","journal-title":"arxiv p rep rint"},{"key":"ref15","article-title":"Logic compatible high-performance ferroelectric transis-tor memory","author":"dutta","year":"2021","journal-title":"ArXiv Preprint"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2966484"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3461662"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3195617"},{"key":"ref17","article-title":"Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices","volume":"abs 1603 7341","author":"tayfun","year":"2016","journal-title":"CoRR"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6463\/aad6f8"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479083"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2709812"},{"key":"ref51","first-page":"896","article-title":"1 Mb 0. 41 µm2, 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing","volume":"49","author":"li","year":"2014","journal-title":"IEEE JSSC"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967059"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2972528"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3567867"},{"key":"ref48","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multi core and manycore architectures","author":"li","year":"2009","journal-title":"Micro"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0733"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref44","article-title":"System-level exploration of in-package wireless communication for multi-chiplet platforms","author":"morillas","year":"2023","journal-title":"ASPDAC"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3230285"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00054"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-022-33629-7"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265014"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3460970"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-022-23116-w"},{"key":"ref3","year":"2020","journal-title":"DPRIVE Building Hardware to Enable Continuous Data Protections"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268337"},{"key":"ref5","first-page":"994","article-title":"NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory","volume":"31","author":"dong","year":"2012","journal-title":"IEEE TCAD"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477325"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3160591"},{"key":"ref37","author":"waterman","year":"2016","journal-title":"Design of the RISC-V Instruction Set Architecture"},{"key":"ref36","author":"s","year":"2023","journal-title":"X-HEEP github repository"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0321-3"},{"key":"ref30","first-page":"1842","article-title":"Meta-Learning with Memory-Augmented Neural Networks","volume":"48","author":"santoro","year":"2016","journal-title":"Proc of the 33rd International Conference on International Conference on Machine Learning"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52688.2022.00885"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3110464"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN55064.2022.9891914"},{"key":"ref1","first-page":"1877","article-title":"Language models are few-shot learners","volume":"33","author":"brown","year":"2020","journal-title":"Advances in neural information processing systems"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317741"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530980"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-020-15254-4"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3039477"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2020.3004989"},{"key":"ref25","first-page":"104c","article-title":"1Mb 0. 41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing","author":"li","year":"2013","journal-title":"2013 Symposiumon VLSI Circuits"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2016.2565262"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720562"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.2994896"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED52811.2021.9502498"},{"key":"ref29","first-page":"151","article-title":"A practical gpu based knn algorithm","author":"kuang","year":"2009","journal-title":"Proceedings The 2009 International Symposium on Computer Science and Computational Technology (ISCSCI2009)"}],"event":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Antwerp, Belgium","start":{"date-parts":[[2023,4,17]]},"end":{"date-parts":[[2023,4,19]]}},"container-title":["2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10136870\/10136706\/10136923.pdf?arnumber=10136923","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T17:49:43Z","timestamp":1695664183000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10136923\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":51,"URL":"https:\/\/doi.org\/10.23919\/date56975.2023.10136923","relation":{},"subject":[],"published":{"date-parts":[[2023,4]]}}}