{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T03:02:16Z","timestamp":1725678136316},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.23919\/date56975.2023.10136932","type":"proceedings-article","created":{"date-parts":[[2023,6,2]],"date-time":"2023-06-02T19:32:57Z","timestamp":1685734377000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["A Novel Delay Calibration Method Considering Interaction between Cells and Wires"],"prefix":"10.23919","author":[{"given":"Leilei","family":"Jin","sequence":"first","affiliation":[{"name":"The National ASIC System Engineering Technology Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiajie","family":"Xu","sequence":"additional","affiliation":[{"name":"The National ASIC System Engineering Technology Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenjie","family":"Fu","sequence":"additional","affiliation":[{"name":"The National ASIC System Engineering Technology Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao","family":"Yan","sequence":"additional","affiliation":[{"name":"The National ASIC System Engineering Technology Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiao","family":"Shi","sequence":"additional","affiliation":[{"name":"School of Computer Science and Engineering, Southeast University,Nanjing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming","family":"Ling","sequence":"additional","affiliation":[{"name":"The National ASIC System Engineering Technology Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Longxing","family":"Shi","sequence":"additional","affiliation":[{"name":"The National ASIC System Engineering Technology Research Center, Southeast University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2018.06.013"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511148"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287658"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"ref20","article-title":"PULPino: A small single-core RISC-V So C[C]","author":"traber","year":"2016","journal-title":"3rd RISC-V Workshop"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2501370"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116256"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2955091"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0294"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218682"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3157981"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2554561"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2687059"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2915324"},{"journal-title":"2008 12 Synopsys","year":"2008","key":"ref7"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218712"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2747937"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2647853"},{"key":"ref6","first-page":"104","article-title":"Performance-and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes","author":"han","year":"2017","journal-title":"Proc ISQED"},{"journal-title":"Designing a Digital Circuit by Correlating Different Static Timing Analyzers","year":"2010","author":"moon","key":"ref5"}],"event":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2023,4,17]]},"location":"Antwerp, Belgium","end":{"date-parts":[[2023,4,19]]}},"container-title":["2023 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10136870\/10136706\/10136932.pdf?arnumber=10136932","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T17:49:59Z","timestamp":1695664199000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10136932\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date56975.2023.10136932","relation":{},"subject":[],"published":{"date-parts":[[2023,4]]}}}