{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:37:42Z","timestamp":1740101862825,"version":"3.37.3"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2810.019"],"award-info":[{"award-number":["2810.019"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.23919\/date56975.2023.10136993","type":"proceedings-article","created":{"date-parts":[[2023,6,2]],"date-time":"2023-06-02T19:32:57Z","timestamp":1685734377000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits"],"prefix":"10.23919","author":[{"given":"Sayandeep","family":"Sanyal","sequence":"first","affiliation":[{"name":"Indian Institute of Technology,Kharagpur"}]},{"given":"Aritra","family":"Hazra","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology,Kharagpur"}]},{"given":"Pallab","family":"Dasgupta","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology,Kharagpur"}]},{"given":"Scott","family":"Morrison","sequence":"additional","affiliation":[{"name":"Texas Instruments,USA"}]},{"given":"Sudhakar","family":"Surendran","sequence":"additional","affiliation":[{"name":"Texas Instruments (India) Pvt. Ltd."}]},{"given":"Lakshmanan","family":"Balasubramanian","sequence":"additional","affiliation":[{"name":"Texas Instruments (India) Pvt. Ltd."}]},{"given":"Mohammad Moshiur","family":"Rahman","sequence":"additional","affiliation":[{"name":"Texas Instruments,USA"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3157686"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045131"},{"key":"ref15","first-page":"337","article-title":"Z3: An Efficient SMT Solver","author":"de moura","year":"2008","journal-title":"Tools and Algorithms for the Construction and Analysis of Systems"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1613\/jair.2347"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID49098.2020.00038"},{"key":"ref10","first-page":"116","author":"mooney","year":"1997","journal-title":"Monte Carlo Simulation"},{"key":"ref2","first-page":"ii","article-title":"A hierarchical interface design methodology and models for SoC IP integration","volume":"2","author":"jou","year":"0","journal-title":"IEEE Int Symp on Circuits and Syst (ISCAS) 2002"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873611"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484656"},{"key":"ref7","first-page":"1","article-title":"IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows","year":"2018","journal-title":"IEEE Std 1685&#x2013;2014 (Revision of IEEE Std 1685&#x2013;2009)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IECON.2015.7392520"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317818"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC48104.2019.9058884"},{"key":"ref6","first-page":"1","article-title":"A machine-readable specification of analog circuits for integration into a validation flow","author":"ma","year":"0","journal-title":"FDL 2011 Proceedings"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240835"}],"event":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2023,4,17]]},"location":"Antwerp, Belgium","end":{"date-parts":[[2023,4,19]]}},"container-title":["2023 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10136870\/10136706\/10136993.pdf?arnumber=10136993","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T17:50:04Z","timestamp":1695664204000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10136993\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date56975.2023.10136993","relation":{},"subject":[],"published":{"date-parts":[[2023,4]]}}}