{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T23:41:53Z","timestamp":1774741313659,"version":"3.50.1"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001667","name":"National Natural Science Foundation of China (NSFC)","doi-asserted-by":"publisher","award":["62334014"],"award-info":[{"award-number":["62334014"]}],"id":[{"id":"10.13039\/501100001667","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,3,25]]},"DOI":"10.23919\/date58400.2024.10546503","type":"proceedings-article","created":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T17:28:02Z","timestamp":1723656482000},"page":"1-6","source":"Crossref","is-referenced-by-count":6,"title":["An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint"],"prefix":"10.23919","author":[{"given":"Lingfeng","family":"Zhou","sequence":"first","affiliation":[{"name":"School of Microelectronics Science and Technology, Sun Yat-sen University,China"}]},{"given":"Shanlin","family":"Xiao","sequence":"additional","affiliation":[{"name":"School of Microelectronics Science and Technology, Sun Yat-sen University,China"}]},{"given":"Huiyao","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics Science and Technology, Sun Yat-sen University,China"}]},{"given":"Jinghai","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics Science and Technology, Sun Yat-sen University,China"}]},{"given":"Zeyang","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Microelectronics Science and Technology, Sun Yat-sen University,China"}]},{"given":"Bohan","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics Science and Technology, Sun Yat-sen University,China"}]},{"given":"Zhiyi","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Microelectronics Science and Technology, Sun Yat-sen University,China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.112130359"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474396"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3025508"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062952"},{"issue":"E80-D","key":"ref6","first-page":"315","article-title":"Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers","volume-title":"IEICE Trans Information & Systems D","volume":"80","author":"Cortadella","year":"1997"},{"key":"ref7","volume-title":"The Balsa Asynchronous Circuit Synthesis System","author":"Bardsley","year":"2000"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.079"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2017.22"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2998911"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2015.104"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2018.00036"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00020"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3038337"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC48570.2021.00013"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2010.11"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00010"},{"key":"ref18","volume-title":"biriscv","year":"2023"},{"key":"ref19","volume-title":"riscv-arch-test","year":"2023"},{"key":"ref20","volume-title":"SiFive E31 Standard Core - High-performance 32-bit embedded RISC-V Core IP","year":"2023"},{"key":"ref21","volume-title":"T-Head XuanTie E907 Processor","year":"2023"},{"key":"ref22","volume-title":"ARM Cortex-A5 Processor Performance and Specification","year":"2023"}],"event":{"name":"2024 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","location":"Valencia, Spain","start":{"date-parts":[[2024,3,25]]},"end":{"date-parts":[[2024,3,27]]}},"container-title":["2024 Design, Automation &amp;amp; Test in Europe Conference &amp;amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10546498\/10546499\/10546503.pdf?arnumber=10546503","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T04:28:05Z","timestamp":1723696085000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10546503\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,25]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date58400.2024.10546503","relation":{},"subject":[],"published":{"date-parts":[[2024,3,25]]}}}