{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T10:08:44Z","timestamp":1764842924535},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002347","name":"Federal Ministry of Education and Research (BMBF, Germany)","doi-asserted-by":"publisher","award":["03ZU1106CA"],"award-info":[{"award-number":["03ZU1106CA"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,3,25]]},"DOI":"10.23919\/date58400.2024.10546668","type":"proceedings-article","created":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T17:28:02Z","timestamp":1723656482000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures"],"prefix":"10.23919","author":[{"given":"Rebecca","family":"Pelke","sequence":"first","affiliation":[{"name":"Institute for Communication Technologies and Embedded Systems, RWTH Aachen University,Germany"}]},{"given":"Jose","family":"Cubero-Cascante","sequence":"additional","affiliation":[{"name":"Institute for Communication Technologies and Embedded Systems, RWTH Aachen University,Germany"}]},{"given":"Nils","family":"Bosbach","sequence":"additional","affiliation":[{"name":"Institute for Communication Technologies and Embedded Systems, RWTH Aachen University,Germany"}]},{"given":"Felix","family":"Staudigl","sequence":"additional","affiliation":[{"name":"Institute for Communication Technologies and Embedded Systems, RWTH Aachen University,Germany"}]},{"given":"Rainer","family":"Leupers","sequence":"additional","affiliation":[{"name":"Institute for Communication Technologies and Embedded Systems, RWTH Aachen University,Germany"}]},{"given":"Jan Moritz","family":"Joseph","sequence":"additional","affiliation":[{"name":"Institute for Communication Technologies and Embedded Systems, RWTH Aachen University,Germany"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/s11432-020-3227-1","article-title":"Breaking the von Neu-mann bottleneck: architecture-level processing-in-memory technology","author":"Zou","year":"2021","journal-title":"Science China Information Sciences"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ted.2017.2699679"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/MCSE.2015.4"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1038\/s41586-022-04992-8"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1145\/3297858.3304049"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ISCA.2016.12"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1145\/3007787.3001140"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/3579371.3589048"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1145\/2964284.2967243"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TCSI.2019.2958568"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/3489517.3530476"},{"key":"ref12","article-title":"X-CHANGR: Changing Mem-ristive Crossbar Mapping for Mitigating Line-Resistance Induced Accuracy Degradation in Deep Neural Networkss","author":"Agrawal","year":"2019","journal-title":"arXiv preprint"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ISLPED52811.2021.9502474"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/JETCAS.2022.3173649"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/3240765.3240825"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref17","article-title":"Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks","author":"Symons","year":"2022","journal-title":"arXiv preprint"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/TC.2021.3122905"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/IEDM.2016.7838346"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/HPCA.2017.55"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/CVPR.2018.00286"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/VLSI-SoC57769.2023.10321873"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.3389\/frai.2021.659060"}],"event":{"name":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2024,3,25]]},"location":"Valencia, Spain","end":{"date-parts":[[2024,3,27]]}},"container-title":["2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10546498\/10546499\/10546668.pdf?arnumber=10546668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T04:31:03Z","timestamp":1723696263000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10546668\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,25]]},"references-count":23,"URL":"https:\/\/doi.org\/10.23919\/date58400.2024.10546668","relation":{},"subject":[],"published":{"date-parts":[[2024,3,25]]}}}