{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:35:25Z","timestamp":1772724925333,"version":"3.50.1"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62102257"],"award-info":[{"award-number":["62102257"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"publisher","award":["2022YFB4500200"],"award-info":[{"award-number":["2022YFB4500200"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,3,25]]},"DOI":"10.23919\/date58400.2024.10546754","type":"proceedings-article","created":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T13:28:02Z","timestamp":1723642082000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["PIMLC: Logic Compiler for Bit-Serial Based PIM"],"prefix":"10.23919","author":[{"given":"Chenyu","family":"Tang","sequence":"first","affiliation":[{"name":"School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Nie","sequence":"additional","affiliation":[{"name":"School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weikang","family":"Qian","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,UM-SJTU Joint Institute and MoE Key Lab of AI,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhezhi","family":"He","sequence":"additional","affiliation":[{"name":"School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"VLSI signal processing; a bit-serial approach","author":"Denyer","year":"1985"},{"key":"ref2","article-title":"A 28-nm compute sram with bit-serial logic\/arithmetic operations for programmable in-memory vector computing","author":"Wang","year":"2019","journal-title":"ISSC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0970"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897985"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3285095"},{"key":"ref9","article-title":"Cacti 5.1","author":"Thoziyoor","year":"2008","journal-title":"tech. rep."},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2012.2185930"},{"key":"ref11","article-title":"Simpler magic: Synthesis and mapping of in-memory logic executed in a single row to improve throughput","author":"Ben-Hur","year":"2019","journal-title":"TCAD"},{"key":"ref12","first-page":"183","article-title":"Xmg-gppic: Efficient and robust general-purpose processing-in-cache with xor-majority-graph","volume-title":"Proceedings of the Great Lakes Symposium on VLSI2023","author":"Nie"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2018.2808959"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/71.993206"},{"issue":"CONF","key":"ref15","article-title":"The epfl combinational benchmark suite","volume-title":"International Workshop on Logic & Synthesis","author":"Amani","year":"2015"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224171"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3462632"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00044"}],"event":{"name":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Valencia, Spain","start":{"date-parts":[[2024,3,25]]},"end":{"date-parts":[[2024,3,27]]}},"container-title":["2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10546498\/10546499\/10546754.pdf?arnumber=10546754","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T18:10:50Z","timestamp":1755281450000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10546754\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,25]]},"references-count":18,"URL":"https:\/\/doi.org\/10.23919\/date58400.2024.10546754","relation":{},"subject":[],"published":{"date-parts":[[2024,3,25]]}}}