{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,12]],"date-time":"2026-07-12T00:09:42Z","timestamp":1783814982613,"version":"3.55.0"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"publisher","award":["2020YFA0711900,2020YFA0711901"],"award-info":[{"award-number":["2020YFA0711900,2020YFA0711901"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62141407,62304052,61974032,61929102,61674042,62090025"],"award-info":[{"award-number":["62141407,62304052,61974032,61929102,61674042,62090025"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004826","name":"Beijing Natural Science Foundation","doi-asserted-by":"publisher","award":["Z220003"],"award-info":[{"award-number":["Z220003"]}],"id":[{"id":"10.13039\/501100004826","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,3,25]]},"DOI":"10.23919\/date58400.2024.10546770","type":"proceedings-article","created":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T17:28:02Z","timestamp":1723656482000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling"],"prefix":"10.23919","author":[{"given":"Tianchen","family":"Gu","sequence":"first","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiaqi","family":"Wang","sequence":"additional","affiliation":[{"name":"Academy of Mathematics and Systems Science, Chinese Academy of Sciences & University of Chinese Academy of Sciences,State Key Laboratory of Scientific and Engineering Computing,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhaori","family":"Bi","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Changhao","family":"Yan","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yajie","family":"Qin","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tao","family":"Cui","sequence":"additional","affiliation":[{"name":"Academy of Mathematics and Systems Science, Chinese Academy of Sciences & University of Chinese Academy of Sciences,State Key Laboratory of Scientific and Engineering Computing,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889371"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2961322"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.04.003"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2284109"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768826"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474253"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3081405"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218757"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3221694"},{"key":"ref10","article-title":"Scalable global optimization via local bayesian optimization","volume":"32","author":"Eriksson","year":"2019","journal-title":"Advances in neural information processing systems"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586172"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3121263"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-32494-1_4"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1002\/zamm.19950750118"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2494218"},{"key":"ref16","first-page":"807","article-title":"A review on subspace methods for nonlinear optimization","volume":"4","author":"Yuan","year":"2014","journal-title":"International Congress of Mathematicians"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s10107-020-01506-0"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/BioCAS.2011.6107808"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2010.5667331"}],"event":{"name":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Valencia, Spain","start":{"date-parts":[[2024,3,25]]},"end":{"date-parts":[[2024,3,27]]}},"container-title":["2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10546498\/10546499\/10546770.pdf?arnumber=10546770","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T04:33:25Z","timestamp":1723696405000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10546770\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,25]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/date58400.2024.10546770","relation":{},"subject":[],"published":{"date-parts":[[2024,3,25]]}}}