{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:52:24Z","timestamp":1780674744047,"version":"3.54.1"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T00:00:00Z","timestamp":1711324800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,3,25]]},"DOI":"10.23919\/date58400.2024.10546797","type":"proceedings-article","created":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T17:28:02Z","timestamp":1723656482000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV"],"prefix":"10.23919","author":[{"given":"Chi","family":"Zhang","sequence":"first","affiliation":[{"name":"ETH Zurich,Integrated Systems Laboratory,Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paul","family":"Scheffler","sequence":"additional","affiliation":[{"name":"ETH Zurich,Integrated Systems Laboratory,Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Thomas","family":"Benz","sequence":"additional","affiliation":[{"name":"ETH Zurich,Integrated Systems Laboratory,Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matteo","family":"Perotti","sequence":"additional","affiliation":[{"name":"ETH Zurich,Integrated Systems Laboratory,Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"University of Bologna,Department of Electrical, Electronic, and Information Engineering,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","first-page":"241:1","article-title":"Sparsity in deep learning: Pruning and growth for efficient inference and training in neural networks","volume":"22","author":"Hoefler","year":"2021","journal-title":"J. Mach. Learn. Res."},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1177\/1094342015593158"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527409"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11515-8_10"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2016.7482073"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137243"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744334"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2015.230"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10136958"},{"key":"ref10","volume-title":"AMBA AXI and ACE Protocol Specification"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP54787.2022.00017"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.8.63"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2049662.2049663"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3437801.3441592"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/PMBS51919.2020.00006"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISPDC.2014.29"},{"key":"ref18","first-page":"1","article-title":"Mac: Memory access coalescer for 3d-stacked memory","volume-title":"Proceedings of the 48th International Conference on Parallel Processing","author":"Wang","year":"2019"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"424","DOI":"10.1145\/3307650.3322254","article-title":"Scu: a gpu stream compaction unit for graph processing","volume-title":"Proceedings of the 46th international symposium on computer architecture","author":"Segura","year":"2019"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527432"}],"event":{"name":"2024 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","location":"Valencia, Spain","start":{"date-parts":[[2024,3,25]]},"end":{"date-parts":[[2024,3,27]]}},"container-title":["2024 Design, Automation &amp;amp; Test in Europe Conference &amp;amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10546498\/10546499\/10546797.pdf?arnumber=10546797","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T04:33:53Z","timestamp":1723696433000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10546797\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,25]]},"references-count":20,"URL":"https:\/\/doi.org\/10.23919\/date58400.2024.10546797","relation":{},"subject":[],"published":{"date-parts":[[2024,3,25]]}}}