{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T16:46:03Z","timestamp":1771605963948,"version":"3.50.1"},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10992720","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-6","source":"Crossref","is-referenced-by-count":7,"title":["FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware"],"prefix":"10.23919","author":[{"given":"Minwoo","family":"Kang","sequence":"first","affiliation":[{"name":"University of California,Berkeley,CA"}]},{"given":"Mingjie","family":"Liu","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA"}]},{"given":"Ghaith Bany","family":"Hamad","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA"}]},{"given":"Syed M.","family":"Suhaib","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA"}]},{"given":"Haoxing","family":"Ren","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA"}]}],"member":"263","reference":[{"key":"ref1","article-title":"GPT-4 Technical Report","author":"Achiam","year":"2023","journal-title":"arXiv preprint"},{"key":"ref2","volume":"abs\/2108.07732","author":"Austin","year":"2021","journal-title":"Program Synthesis with Large Language Models"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD58807.2023.10299874"},{"key":"ref4","volume":"abs\/2107.03374","author":"Chen","year":"2021","journal-title":"Evaluating Large Language Models Trained on Code"},{"key":"ref5","article-title":"The Llama 3 Herd of Models","author":"Dubey","year":"2024","journal-title":"arXiv preprint"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691792"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44778.2020.9325264"},{"key":"ref8","volume":"abs\/2312.11805","year":"2023","journal-title":"Gemini: A family of highly capable multimodal models"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546729"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD58807.2023.10299852"},{"key":"ref11","volume-title":"Measuring massive multitask language understanding","author":"Hendrycks","year":"2021"},{"key":"ref12","volume":"abs\/2401.04088","author":"Jiang","year":"2024","journal-title":"Mixtral of experts"},{"key":"ref13","article-title":"Jeyavijayan Rajendran Texas AM University, University of New South Wales, University of Calgary, and New York University","volume-title":"Llm-assisted generation of hardware assertions","volume":"abs\/2306.14027","author":"Kande","year":"2023"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323681"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3600006.3613165"},{"key":"ref16","volume":"abs\/2311.00176","author":"Liu","year":"2023","journal-title":"Chipnemo: Domain-adapted llms for chip design"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTS60656.2024.10538589"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323812"},{"key":"ref19","article-title":"Codegen: An open large language model for code with multi-turn program synthesis","author":"Nijkamp","year":"2023","journal-title":"ICLR"},{"key":"ref20","volume-title":"OpenTitan. Opentitan","year":"2024"},{"key":"ref21","volume":"abs\/2309.09437","year":"2023","journal-title":"Marcelo Orenes-Vera, Margaret Martonosi, and David Wentzlaff. Using llms to facilitate formal verification of rtl"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430634"},{"key":"ref23","article-title":"Towards Improving Verification Productivity with Circuit-Aware Translation of Natural Language to SystemVerilog Assertions","volume-title":"First International Workshop on Deep Learning-aided Verification","author":"Sun","year":"2023"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3643681"},{"key":"ref25","volume":"abs\/2312.01022","author":"Thorat","year":"2023","journal-title":"Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657353"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714857"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","location":"Lyon, France","start":{"date-parts":[[2025,3,31]]},"end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10992720.pdf?arnumber=10992720","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:32:10Z","timestamp":1747891930000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10992720\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":27,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10992720","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}