{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T04:05:24Z","timestamp":1747973124278,"version":"3.41.0"},"reference-count":29,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10992760","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Comprehensive RISC- V Floating-Point Verification: Efficient Coverage Models and Constraint-Based Test Generation"],"prefix":"10.23919","author":[{"given":"Tianyao","family":"Lu","sequence":"first","affiliation":[{"name":"College of Information Science and Electronic Engineering, Zhejiang University,Hangzhou,China,310027"}]},{"given":"Anlin","family":"Liu","sequence":"additional","affiliation":[{"name":"College of Information Science and Electronic Engineering, Zhejiang University,Hangzhou,China,310027"}]},{"given":"Bingjie","family":"Xia","sequence":"additional","affiliation":[{"name":"College of Information Science and Electronic Engineering, Zhejiang University,Hangzhou,China,310027"}]},{"given":"Peng","family":"Liu","sequence":"additional","affiliation":[{"name":"College of Information Science and Electronic Engineering, Zhejiang University,Hangzhou,China,310027"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3097174"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1137\/S0036144595293959"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/sj.413.0386"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1277900"},{"issue":"9","key":"ref5","first-page":"3141","article-title":"A RISC-V test sequences generation method based on instruction generation constraints","volume":"45","author":"Liu","year":"2023","journal-title":"Journal of Electronics and Information Technology"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.scico.2015.10.012"},{"volume-title":"The RISC-V instruction set manual, volume I","year":"2019","author":"Waterman","key":"ref7"},{"volume-title":"RISC-V DV","key":"ref8"},{"key":"ref9","first-page":"1","article-title":"IEEE standard for floating-point arithmetic","year":"2008","journal-title":"IEEE Std 754\u20132008"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176425"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"848","DOI":"10.1145\/2024724.2024914","article-title":"Learning microarchitectural behaviors to improve stimuli generation quality","volume-title":"Proceedings of the 48th Design Automation Conference","author":"Katz","year":"2011"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-70389-3_15"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775907"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116198"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714912"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH58626.2023.00018"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-87181-9"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137166"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2003.1252469"},{"volume-title":"Berkeley testfloat","key":"ref20"},{"volume-title":"RISC-V ISA TESTS","key":"ref21"},{"volume-title":"RISC-V Architecture Test SIG","key":"ref22"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116193"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774771"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2023.3262741"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ITC51657.2024.00015"},{"key":"ref28","first-page":"41","article-title":"QEMU, a fast and portable dynamic translator","volume-title":"FREENIX Track: USENIX Annual Technical Conference","author":"Bellard","year":"2005"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"}],"event":{"name":"2025 Design, Automation &amp; Test in Europe Conference (DATE)","start":{"date-parts":[[2025,3,31]]},"location":"Lyon, France","end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation &amp;amp; Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10992760.pdf?arnumber=10992760","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:53:06Z","timestamp":1747893186000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10992760\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":29,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10992760","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}