{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T17:03:16Z","timestamp":1770742996666,"version":"3.49.0"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10992815","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint"],"prefix":"10.23919","author":[{"given":"H. Ekin","family":"Sumbul","sequence":"first","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Arne","family":"Symons","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Lita","family":"Yang","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Huichu","family":"Liu","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Tony F.","family":"Wu","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Matheus Trevisan","family":"Moreira","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Debabrata","family":"Mohapatra","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Abhinav","family":"Agarwal","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Kaushik","family":"Ravindran","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Chris","family":"Thompson","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Yuecheng","family":"Li","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]},{"given":"Edith","family":"Beigne","sequence":"additional","affiliation":[{"name":"Reality Labs,Meta,Menlo Park,CA,USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR46437.2021.00013"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776486"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720568"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51529.2024.00058"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC56328.2022.10013108"},{"key":"ref6","article-title":"Successful 3DIC Multi-Die Silicon Sys-tem Design Using Synopsys 3DIC and Ansys Multiphysics Analysis","author":"Larsen","year":"2022","journal-title":"Microelectronics Packaging and Test Engineering Council (MEPTEC), Road to Chiplets: Design Integration"},{"key":"ref7","article-title":"3D-IC (3DHI) Design Challenges","author":"Park","year":"2022","journal-title":"Microelectronics Packaging and Test Engineering Council (MEPTEC), Road to Chiplets: Design Integration"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3299564"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3011042"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454529"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116297"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772810"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185381"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3202254"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","location":"Lyon, France","start":{"date-parts":[[2025,3,31]]},"end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10992815.pdf?arnumber=10992815","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T06:04:09Z","timestamp":1747893849000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10992815\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":14,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10992815","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}