{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,17]],"date-time":"2026-01-17T07:47:49Z","timestamp":1768636069383,"version":"3.49.0"},"reference-count":36,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100014188","name":"Ministry of Science and ICT","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10992823","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T13:36:35Z","timestamp":1747834595000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["Improving Address Translation in Tagless DRAM Cache by Caching PTE Pages"],"prefix":"10.23919","author":[{"given":"Osang","family":"Kwon","sequence":"first","affiliation":[{"name":"Sungkyunkwan University,Department of Electrical and Computer Engineering,Suwon,Republic of Korea"}]},{"given":"Yongho","family":"Lee","sequence":"additional","affiliation":[{"name":"Sungkyunkwan University,Department of Electrical and Computer Engineering,Suwon,Republic of Korea"}]},{"given":"Seokin","family":"Hong","sequence":"additional","affiliation":[{"name":"Sungkyunkwan University,Department of Electrical and Computer Engineering,Suwon,Republic of Korea"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3342195.3387518"},{"key":"ref2","author":"Anthony","year":"2013","journal-title":"Intel unveils 72-core x86 knights landing cpu for exascale supercomputing"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815970"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/68182.68193"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3185768.3185771"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582021"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628089"},{"key":"ref9","volume-title":"5-Level Paging and 5-Level EPT White Paper, Intel","year":"2018"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446068"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"325","DOI":"10.1145\/3656019.3676900","article-title":"Rethinking page table structure for fast address translation in gpus: A fixed-size hashed page table","volume-title":"Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques","author":"Jang","year":"2024"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.51"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485957"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416642"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"1178","DOI":"10.1145\/3613424.3614276","article-title":"Victima: Drastically increasing address translation reach by leveraging underutilized cache resources","volume-title":"Proceedings of the 56th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Kanellopoulos","year":"2023"},{"key":"ref16","article-title":"Virtuoso: An open-source, comprehensive and modular simulation framework for virtual memory research","volume-title":"arXiv preprint","author":"Kanellopoulos","year":"2024"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071016"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00076"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00013"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530540"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750383"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"454","DOI":"10.1145\/2155620.2155673","article-title":"Efficiently enabling conventional block sizes for very large die-stacked dram caches","volume-title":"Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Loh","year":"2011"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188677"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582063"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807626"},{"key":"ref26","article-title":"Deep learning recommendation model for personalization and recommendation systems","author":"Naumov","year":"2019","journal-title":"arXiv preprint"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.30"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507718"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00029"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995911"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3624062.3624195"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378493"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS51385.2021.00012"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1145\/3613424.3614256","article-title":"Demystifying cxl memory with genuine cxl-ready systems and devices","volume-title":"Proceedings of the 56th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Sun","year":"2023"},{"key":"ref36","article-title":"Xsbench-the development and verification of a performance abstraction for monte carlo reactor analysis","author":"Tramm","year":"2014","journal-title":"The Role of Reactor Physics toward a Sustainable Future (PHYSOR)"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","location":"Lyon, France","start":{"date-parts":[[2025,3,31]]},"end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10992823.pdf?arnumber=10992823","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,16]],"date-time":"2026-01-16T20:47:19Z","timestamp":1768596439000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10992823\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":36,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10992823","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}