{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T06:40:01Z","timestamp":1747896001913,"version":"3.41.0"},"reference-count":26,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10992962","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs"],"prefix":"10.23919","author":[{"given":"Cyril","family":"Koenig","sequence":"first","affiliation":[{"name":"ETH Zurich,Integrated Systems Laboratory"}]},{"given":"Enrico","family":"Zelioli","sequence":"additional","affiliation":[{"name":"ETH Zurich,Integrated Systems Laboratory"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"ETH Zurich,Zurich,Switzerland"}]}],"member":"263","reference":[{"volume-title":"Introducing Jetson Xavier NX, the World\u2019s Small-est AI Supercomputer","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589349"},{"volume-title":"RISC-V","key":"ref3","article-title":"RISC-V IOMMU Architecture Specification"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3140674"},{"journal-title":"Attention in SRAM on Tenstorrent Grayskull","year":"2024","author":"Th\u00fcning","key":"ref5"},{"journal-title":"Occamy: A 432-Core 28.1 DP-GFLOP\/s\/W 83","author":"Paulin","key":"ref6"},{"key":"ref7","article-title":"Open-source RISC-V Input\/Output Memory Management Unit (IOMMU) IP","author":"Rodr\u00edguez","year":"2023","journal-title":"RISC-V Summit Europe, Barcelona, 5\u20139th June 2023"},{"volume-title":"Zero Day Labs","key":"ref8","article-title":"RISC-V IOMMU IP"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.19"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00036"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3289186"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/tc.2021.3107726"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3027900"},{"journal-title":"OpenMP Architecture Review Board","article-title":"OpenMP Application Program Interface Version 5.0","year":"2018","key":"ref15"},{"journal-title":"Linux RISC-V IOMMU Support","author":"Jeznach","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/P3HPC49587.2019.00012"},{"key":"ref18","article-title":"Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP","volume-title":"ArXiv","volume":"abs\/2206.01901","author":"Zuckerman","year":"2022"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2016.7482091"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3563766.3564110"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3295816.3295821"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00052"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465921"},{"key":"ref24","article-title":"The Price of Safety: Evaluating IOMMU Performance","volume-title":"Ottawa Linux Symposium (OLS)","author":"Ben-Yehuda","year":"2007"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.32"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173175"}],"event":{"name":"2025 Design, Automation &amp; Test in Europe Conference (DATE)","start":{"date-parts":[[2025,3,31]]},"location":"Lyon, France","end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation &amp;amp; Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10992962.pdf?arnumber=10992962","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:58:37Z","timestamp":1747893517000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10992962\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":26,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10992962","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}