{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:33:36Z","timestamp":1763724816610,"version":"3.41.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92473203,92373206"],"award-info":[{"award-number":["92473203,92373206"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10993024","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy"],"prefix":"10.23919","author":[{"given":"Jiaping","family":"Tang","sequence":"first","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Jianan","family":"Mu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Silin","family":"Liu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Zizhen","family":"Liu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Feng","family":"Gu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Xinyu","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Leyan","family":"Wang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Shengwen","family":"Liang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Jing","family":"Ye","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]},{"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China"}]}],"member":"263","reference":[{"journal-title":"Road vehicles - Functional Safety - Part 4: Product development at the system level","key":"ref1","article-title":"ISO 26262"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/itc50671.2022.00040"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/itc50671.2022.00036"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2008.2000254"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ftcs.1994.315656"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ftcs.1997.614074"},{"volume-title":"Iverilog","author":"Williams","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ets.2011.58"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ets.2011.58"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3243490"},{"key":"ref12","first-page":"1","article-title":"Extending Verilator to Enable Fault Simulation","volume-title":"MBMV 2021; 24th Workshop","author":"Kaja","year":"2021"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3587135.3591435"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.7799"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/simsym.2000.844911"},{"key":"ref16","first-page":"1","article-title":"IEEE Standard for Verilog Hardware Description Language","year":"2006","journal-title":"IEEE Std 1364\u20132005 (Revision of IEEE Std 1364\u20132001)"},{"key":"ref18","first-page":"1","article-title":"Extending Verilator to Enable Fault Simulation","author":"Kaja","year":"2021","journal-title":"MBMV 2021; 24th Workshop"},{"volume-title":"ucb-bar","key":"ref24"},{"volume-title":"crypto-accelerator","key":"ref26"},{"volume-title":"Yosys: A Framework for Verilog RTL Synthesis","key":"ref29"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/itc50671.2022.00040"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/itc50671.2022.00036"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3623278.3624750"}],"event":{"name":"2025 Design, Automation &amp; Test in Europe Conference (DATE)","start":{"date-parts":[[2025,3,31]]},"location":"Lyon, France","end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation &amp;amp; Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10993024.pdf?arnumber=10993024","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:48:00Z","timestamp":1747892880000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10993024\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10993024","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}