{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T00:05:44Z","timestamp":1780445144531,"version":"3.54.1"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10993030","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":4,"title":["Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables"],"prefix":"10.23919","author":[{"given":"Subhadip","family":"Ghosh","sequence":"first","affiliation":[{"name":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Endalk Y.","family":"Gebru","sequence":"additional","affiliation":[{"name":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chandramouli V.","family":"Kashyap","sequence":"additional","affiliation":[{"name":"Cadence Design Systems,Portland,OR,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ramesh","family":"Harjani","sequence":"additional","affiliation":[{"name":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[{"name":"University of Minnesota,Department of Electrical and Computer Engineering,Minneapolis,MN,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/43.44506"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-009-0279-4_9"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217566"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.102664"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2012.01.003"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3522738"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3101691"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.905671"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586139"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116200"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218757"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247739"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1706.03762"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/82.661648"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-018-1131-7"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1953.274449"},{"key":"ref17","volume-title":"HT FHNW EIT: Analog and mixed-signal circuits and signal processing","author":"Schmid"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/P16-1162"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.535416"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1017\/9781108125840"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768826"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.04.003"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","location":"Lyon, France","start":{"date-parts":[[2025,3,31]]},"end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10993030.pdf?arnumber=10993030","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T17:35:37Z","timestamp":1750354537000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10993030\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10993030","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}