{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T06:10:09Z","timestamp":1747894209496,"version":"3.41.0"},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003347","name":"Fudan University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10993073","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["PreVV: Eliminating Store Queue via Premature Value Validation for Dataflow Circuit on FPGA"],"prefix":"10.23919","author":[{"given":"Kuangjie","family":"Zou","sequence":"first","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips & Systems,Shanghai,China"}]},{"given":"Yifan","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips & Systems,Shanghai,China"}]},{"given":"Zicheng","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips & Systems,Shanghai,China"}]},{"given":"Guoyu","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips & Systems,Shanghai,China"}]},{"given":"Jianli","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips & Systems,Shanghai,China"}]},{"given":"Kun","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips & Systems,Shanghai,China"}]},{"given":"Jun","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips & Systems,Shanghai,China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1028176.1006709"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/micro.2018.00042"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/micro.2006.26"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3126525"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293914"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/icfpt47387.2019.00031"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3071631"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3543622.3573050"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3626202.3637570"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3626202.3637556"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3640537.3641581"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2020.3012866"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2022.3188136"},{"volume-title":"A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthe-sis","year":"2023","author":"Szafarczyk","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375391"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/icfpt56656.2022.9974425"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"volume-title":"Dynamic Scheduling in High-Level Compilation for Adaptive Computers","year":"2011","author":"Gadke-Lutjens","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430572"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/12.48862"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3065902"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/fpl57034.2022.00046"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/BF03356742"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/800110.803575"},{"key":"ref25","first-page":"1","article-title":"Polly-polyhedral optimization in LLVM","volume-title":"Proc. 1st Int. Workshop Polyhedral Compilation Techniques (IMPACT)","author":"Grosser"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM57271.2023.00055"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3626202.3637595"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","start":{"date-parts":[[2025,3,31]]},"location":"Lyon, France","end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10993073.pdf?arnumber=10993073","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:31:21Z","timestamp":1747891881000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10993073\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":27,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10993073","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}