{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T15:32:27Z","timestamp":1775230347560,"version":"3.50.1"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2021YFA1003602"],"award-info":[{"award-number":["2021YFA1003602"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10993091","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["FAMERS: An FPGA Accelerator for Memory-Efficient Edge-Rendered 3D Gaussian Splatting"],"prefix":"10.23919","author":[{"given":"Yuanfang","family":"Wang","sequence":"first","affiliation":[{"name":"State Key Lab of Integrated Chips & Systems, and School of Microelectronics, Fudan University,Shanghai,China"}]},{"given":"Yu","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Lab of Integrated Chips & Systems, and School of Microelectronics, Fudan University,Shanghai,China"}]},{"given":"Jianli","family":"Chen","sequence":"additional","affiliation":[{"name":"State Key Lab of Integrated Chips & Systems, and School of Microelectronics, Fudan University,Shanghai,China"}]},{"given":"Jun","family":"Yu","sequence":"additional","affiliation":[{"name":"State Key Lab of Integrated Chips & Systems, and School of Microelectronics, Fudan University,Shanghai,China"}]},{"given":"Kun","family":"Wang","sequence":"additional","affiliation":[{"name":"State Key Lab of Integrated Chips & Systems, and School of Microelectronics, Fudan University,Shanghai,China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3503250"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3528223.3530127"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3592433"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1109\/CVPR52733.2024.02052","volume-title":"Compact 3D Gaussian Representation for Radiance Field","author":"Lee","year":"2024"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/cvpr52733.2024.00985"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3651282"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-72980-5_10"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3620666.3651385"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2019.2939726"},{"key":"ref10","article-title":"NVIDIA Nsight Systems","year":"2025","journal-title":"NVIDIA Developer"},{"key":"ref11","article-title":"Nsight Compute | NVIDIA Developer | NVIDIA Developer","year":"2025"},{"key":"ref12","article-title":"RadSplat: Radiance Field-Informed Gaussian Splatting for Robust Real-Time Rendering with 900+ FPS","author":"Niemeyer","year":"2024","journal-title":"arXiv"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/hpca51647.2021.00017"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/fccm57271.2023.00055"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/asp-dac58780.2024.10473990"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3072959.3073599"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/cvpr52688.2022.00539"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3272127.3275084"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","location":"Lyon, France","start":{"date-parts":[[2025,3,31]]},"end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10993091.pdf?arnumber=10993091","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:45:17Z","timestamp":1747892717000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10993091\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":18,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10993091","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}