{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T04:05:16Z","timestamp":1747973116019,"version":"3.41.0"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92373207"],"award-info":[{"award-number":["92373207"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003347","name":"State Key Laboratory of Integrated Chips and Systems at Fudan University","doi-asserted-by":"publisher","award":["SKLICS-Z202404"],"award-info":[{"award-number":["SKLICS-Z202404"]}],"id":[{"id":"10.13039\/501100003347","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100022963","name":"Key Research and Development Program of Zhejiang Province","doi-asserted-by":"publisher","award":["2024C01111"],"award-info":[{"award-number":["2024C01111"]}],"id":[{"id":"10.13039\/100022963","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10993190","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis"],"prefix":"10.23919","author":[{"given":"Hongyang","family":"Pan","sequence":"first","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Circuits and Systems,Shanghai,China"}]},{"given":"Keren","family":"Zhu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Circuits and Systems,Shanghai,China"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Circuits and Systems,Shanghai,China"}]},{"given":"Zhufei","family":"Chu","sequence":"additional","affiliation":[{"name":"Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Circuits and Systems,Shanghai,China"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1007\/978-3-030-60488-2"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/DATE.2012.6176724"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TCAD.2006.882119"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1145\/1723112.1723144"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/DAC56929.2023.10247838"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1145\/1117201.1117208"},{"key":"ref7","article-title":"Lut mapping and optimization for majority-inverter graphs","volume-title":"Proceedings of the 25th International Workshop on Logic & Synthesis (IWLS)","author":"Haaswijk","year":"2016"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/TCAD.2018.2878187"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TCAD.2024.3457378"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1145\/296399.296425"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.23919\/DATE48585.2020.9116379"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ISMVL.2017.44"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ICCAD57390.2023.10323691"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/TCAD.2023.3337279"},{"volume-title":"EPFL combinational benchmark suite","year":"2023","key":"ref15"},{"year":"2023","author":"Mishchenko","journal-title":"ABC: System for sequential logic synthesis and formal verification","key":"ref16"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TCAD.2019.2925392"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.23919\/DATE56975.2023.10137287"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/TCAD.2019.2897703"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/ASP-DAC52403.2022.9712526"},{"volume-title":"Mockturtle","year":"2024","key":"ref21"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/FPL.2016.7577306"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1145\/2068716.2068720"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","start":{"date-parts":[[2025,3,31]]},"location":"Lyon, France","end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10993190.pdf?arnumber=10993190","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:45:16Z","timestamp":1747892716000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10993190\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":23,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10993190","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}