{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T04:05:25Z","timestamp":1747973125319,"version":"3.41.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.23919\/date64628.2025.10993237","type":"proceedings-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:36:35Z","timestamp":1747848995000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Word-Level Counterexample Reduction Methods for Hardware Verification"],"prefix":"10.23919","author":[{"given":"Zhiyuan","family":"Yan","sequence":"first","affiliation":[{"name":"Microelectronics Thrust, The Hong Kong University of Science and Technology (Guangzhou)"}]},{"given":"Hongce","family":"Zhang","sequence":"additional","affiliation":[{"name":"Microelectronics Thrust, The Hong Kong University of Science and Technology (Guangzhou)"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1145\/2966986.2980087"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/1592434.1592438"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1007\/3-540-48683-6_8"},{"year":"2020","author":"Preiner","journal-title":"Hardware model checking competition 2020","key":"ref4"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1007\/978-3-642-14295-6_5"},{"year":"2007","author":"Biere","journal-title":"The AIGER and-inverter graph (AIG) format version 20071012","key":"ref6"},{"key":"ref7","article-title":"A toolbox for counter-example analysis and optimization","volume-title":"Proc. of IWLS","volume":"13","author":"Mishchenko","year":"2013"},{"key":"ref8","first-page":"125","article-title":"Efficient implementation of property directed reachability","author":"E\u00e9n","year":"2011","journal-title":"2011 Formal Methods in Computer-Aided Design (FMCAD)"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1007\/978-3-030-81688-9_22"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1007\/978-3-030-45190-5_23"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.3233\/SAT190101"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1007\/978-3-642-22110-1_14"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1007\/978-3-540-78800-3_24"},{"issue":"2","key":"ref14","first-page":"1","article-title":"The yices smt solver","volume-title":"Tool paper at","volume":"2","author":"Dutertre","year":"2006"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.23919\/DATE.2019.8715289"},{"key":"ref16","article-title":"Extracting small unsatisfiable cores from unsatisfiable boolean formula","volume":"3","author":"Zhang","year":"2003","journal-title":"SAT"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1007\/978-3-319-10575-8_11"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1007\/10722167_15"},{"key":"ref19","article-title":"Effective pre-silicon verification of processor cores by breaking the bounds of symbolic quick error detection","author":"Ganesan","year":"2021","journal-title":"arXiv preprint"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.23919\/DATE.2018.8341979"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1007\/3-540-58179-0_44"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1007\/978-3-030-39322-9_10"}],"event":{"name":"2025 Design, Automation & Test in Europe Conference (DATE)","start":{"date-parts":[[2025,3,31]]},"location":"Lyon, France","end":{"date-parts":[[2025,4,2]]}},"container-title":["2025 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10992638\/10992588\/10993237.pdf?arnumber=10993237","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:54:11Z","timestamp":1747893251000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10993237\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date64628.2025.10993237","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]}}}