{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T06:01:02Z","timestamp":1780639262433,"version":"3.54.1"},"reference-count":35,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,20]]},"DOI":"10.23919\/date69613.2026.11539066","type":"proceedings-article","created":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T19:53:10Z","timestamp":1780602790000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Increasing the Efficiency of Associative Processor Architectures via CMOS-Compatible Hybridization"],"prefix":"10.23919","author":[{"given":"Socrates S.","family":"Wong","sequence":"first","affiliation":[{"name":"Cornell University,Ithaca,NY,USA,14850"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cecilio C.","family":"Tamarit","sequence":"additional","affiliation":[{"name":"Cornell University,Ithaca,NY,USA,14850"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohammad M.","family":"Sharifi","sequence":"additional","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA,46556"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zephan","family":"Enciso","sequence":"additional","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA,46556"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dayane","family":"Reis","sequence":"additional","affiliation":[{"name":"University of South Florida,Tampa,FL,USA,33620"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael","family":"Niemier","sequence":"additional","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA,46556"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"X. Sharon","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Notre Dame,Notre Dame,IN,USA,46556"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jos\u00e9 F.","family":"Mart\u00ednez","sequence":"additional","affiliation":[{"name":"Cornell University,Ithaca,NY,USA,14850"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3142239"},{"key":"ref2","first-page":"118","article-title":"Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory","volume-title":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","author":"Breyer"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527435"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00054"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522314"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MNANO.2021.3098218"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720495"},{"key":"ref8","first-page":"36.4.1","article-title":"Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory","volume-title":"2020 IEEE International Electron Devices Meeting (IEDM)","author":"Dutta"},{"key":"ref9","first-page":"1","article-title":"A Hybrid CMOS-Memristor Spiking Neural Network Supporting Multiple Learning Rules","volume-title":"IEEE Transactions on Neural Networks and Learning Systems","author":"Florini","year":"2022"},{"key":"ref10","volume-title":"Content-Addressable Parallel Processors","author":"Foster","year":"1976"},{"key":"ref11","first-page":"802","article-title":"Floatpim: In-memory acceleration of deep neural network training with high precision","author":"Imani","year":"2019","journal-title":"2019 ACM\/IEEE 46th Annual International Symposium on Computer Architecture (ISCA)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927141"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2952544"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM50854.2024.10873370"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715198"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280845"},{"key":"ref18","article-title":"The gem5 Simulator: Version 20.0+","author":"Lowe-Power","year":"2020"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2022.3181925"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676699"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510622"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45625.2022.10019459"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346181"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2019.2930284"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IMW48823.2020.9108150"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2018.8399771"},{"key":"ref27","first-page":"74","article-title":"Scaling equations for the accurate prediction of cmos device performance from 180nm to 7nm","volume-title":"Integration","volume":"58","author":"Stillmaker","year":"2017"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203889"},{"key":"ref29","first-page":"1356","article-title":"The RISC-V Instruction Set Manual","volume":"I","author":"Waterman","year":"2011"},{"key":"ref30","first-page":"1","article-title":"PUMICE: Processing-using-Memory Integration with a Scalar Pipeline for Symbiotic Execution","volume-title":"2023 60th ACM\/IEEE Design Automation Conference (DAC)","author":"Wong"},{"issue":"2","key":"ref31","first-page":"148","article-title":"Resistive Associative Processor","volume-title":"IEEE Computer Architecture Letters","volume":"14","author":"Yavits","year":"2015"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.220"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2889225"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00074"}],"event":{"name":"2026 Design, Automation & Test in Europe Conference (DATE)","location":"Verona, Italy","start":{"date-parts":[[2026,4,20]]},"end":{"date-parts":[[2026,4,22]]}},"container-title":["2026 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11539023\/11539024\/11539066.pdf?arnumber=11539066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:10:07Z","timestamp":1780636207000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11539066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,20]]},"references-count":35,"URL":"https:\/\/doi.org\/10.23919\/date69613.2026.11539066","relation":{},"subject":[],"published":{"date-parts":[[2026,4,20]]}}}