{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T06:01:37Z","timestamp":1780639297529,"version":"3.54.1"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,20]]},"DOI":"10.23919\/date69613.2026.11539069","type":"proceedings-article","created":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T19:53:10Z","timestamp":1780602790000},"page":"1-3","source":"Crossref","is-referenced-by-count":0,"title":["Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System Simulation"],"prefix":"10.23919","author":[{"given":"Xuguang","family":"Yuan","sequence":"first","affiliation":[{"name":"Tsinghua University,School of Integrated Circuits, BNRist,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiangyuan","family":"Gu","sequence":"additional","affiliation":[{"name":"Tsinghua University,School of Integrated Circuits, BNRist,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qidie","family":"Wu","sequence":"additional","affiliation":[{"name":"Tsinghua University,School of Integrated Circuits, BNRist,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yang","family":"Hu","sequence":"additional","affiliation":[{"name":"Tsinghua University,School of Integrated Circuits, BNRist,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[{"name":"Tsinghua University,School of Integrated Circuits, BNRist,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shouyi","family":"Yin","sequence":"additional","affiliation":[{"name":"Tsinghua University,School of Integrated Circuits, BNRist,Beijing,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00014"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2016.348"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631529"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358302"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2025.3596452"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3207195"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI51249.2020.00017"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS58208.2023.10314935"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586229"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3477206.3477459"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137080"},{"key":"ref12","article-title":"Rapidchiplet: A toolchain for rapid design space exploration of chiplet architectures","author":"Iff","year":"2023"},{"key":"ref13","article-title":"Switchboard: An open-source framework for modular simulation of large hardware systems","author":"Herbst","year":"2024"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546547"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2970019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32696.2021.00061"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51529.2024.00262"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4550075"}],"event":{"name":"2026 Design, Automation &amp; Test in Europe Conference (DATE)","location":"Verona, Italy","start":{"date-parts":[[2026,4,20]]},"end":{"date-parts":[[2026,4,22]]}},"container-title":["2026 Design, Automation &amp;amp; Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11539023\/11539024\/11539069.pdf?arnumber=11539069","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:12:45Z","timestamp":1780636365000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11539069\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,20]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/date69613.2026.11539069","relation":{},"subject":[],"published":{"date-parts":[[2026,4,20]]}}}