{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T06:00:52Z","timestamp":1780639252895,"version":"3.54.1"},"reference-count":48,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,20]]},"DOI":"10.23919\/date69613.2026.11539366","type":"proceedings-article","created":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T19:53:10Z","timestamp":1780602790000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Scalable Second-Order Optimizer for Full-Chip Inverse Lithography Techniques"],"prefix":"10.23919","author":[{"given":"Su","family":"Zheng","sequence":"first","affiliation":[{"name":"Chinese University of Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ziyang","family":"Yu","sequence":"additional","affiliation":[{"name":"Chinese University of Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"Chinese University of Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Martin","family":"Wong","sequence":"additional","affiliation":[{"name":"Hong Kong Baptist University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2020.11.001"},{"key":"ref2","article-title":"LithoBench: Benchmarking ai computational lithography for semiconductor manufacturing","volume-title":"Proc. NeurIPS","author":"Zheng"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742114"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2017.8203477"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203763"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218530"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3309745"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3656254"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3655680"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3378600"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676764"},{"key":"ref12","first-page":"81","article-title":"An efficient rule-based opc approach using a drc tool for 0.18\/spl mu\/m asic","volume-title":"Proc. ISQED","author":"Park"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1117\/12.772790"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1117\/12.2194755"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001358"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1045"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2514082"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1045"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2024.3499909"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISEDA62518.2024.10617951"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11133367"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1117\/12.632366"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593163"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474212"},{"key":"ref25","article-title":"Efficient ilt via multilevel lithography simulation","volume-title":"Proc. DAC","author":"Sun"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3323164"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657309"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676763"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415705"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1117\/1.JMM.20.3.030901"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633315"},{"key":"ref32","article-title":"Adam: A method for stochastic optimization","author":"Kingma","year":"2014"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v35i12.17275"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1098\/rspa.1951.0158"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/BF01589116"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1080\/03610918908812806"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1016\/j.apnum.2007.01.003"},{"key":"ref38","article-title":"Sophia: A scalable stochastic second-order optimizer for language model pre-training","author":"Liu","year":"2023"},{"key":"ref39","article-title":"Openroad flow","year":"2020"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2021.3096794"},{"key":"ref41","article-title":"Ibex risc-v core","year":"2017"},{"key":"ref42","article-title":"Picorv32 - a size-optimized risc-v cpu","year":"2019"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3326334"},{"key":"ref44","article-title":"Nangate 45nm library"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2021.3109556"},{"key":"ref46","article-title":"Pytorch: An imperative style, high-performance deep learning library","volume-title":"Advances in neural information processing systems","volume":"32","author":"Paszke"},{"key":"ref47","article-title":"OpenILT: An open source inverse lithography technique framework","volume-title":"Proc. ASICON","author":"Zheng"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691131"}],"event":{"name":"2026 Design, Automation &amp; Test in Europe Conference (DATE)","location":"Verona, Italy","start":{"date-parts":[[2026,4,20]]},"end":{"date-parts":[[2026,4,22]]}},"container-title":["2026 Design, Automation &amp;amp; Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11539023\/11539024\/11539366.pdf?arnumber=11539366","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:09:27Z","timestamp":1780636167000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11539366\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,20]]},"references-count":48,"URL":"https:\/\/doi.org\/10.23919\/date69613.2026.11539366","relation":{},"subject":[],"published":{"date-parts":[[2026,4,20]]}}}