{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T06:02:03Z","timestamp":1780639323999,"version":"3.54.1"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,20]]},"DOI":"10.23919\/date69613.2026.11539455","type":"proceedings-article","created":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T19:53:10Z","timestamp":1780602790000},"page":"1-3","source":"Crossref","is-referenced-by-count":0,"title":["Synthesizing Mixed-Mode Operations for Memristors using Majority Decomposition"],"prefix":"10.23919","author":[{"given":"Felix","family":"Bayhurst","sequence":"first","affiliation":[{"name":"University of Stuttgart,Institute of Computer Architecture and Computer Engineering,Stuttgart,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Li-Wei","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Stuttgart,Institute of Computer Architecture and Computer Engineering,Stuttgart,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kefeng","family":"Li","sequence":"additional","affiliation":[{"name":"Institute for Solid State Physics Leibniz Institute of Photonic Technology and University of Jena,Jena,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Heidemarie","family":"Kr\u00fcger","sequence":"additional","affiliation":[{"name":"Institute for Solid State Physics Leibniz Institute of Photonic Technology and University of Jena,Jena,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nan","family":"Du","sequence":"additional","affiliation":[{"name":"Institute for Solid State Physics Leibniz Institute of Photonic Technology and University of Jena,Jena,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ilia","family":"Polian","sequence":"additional","affiliation":[{"name":"University of Stuttgart,Institute of Computer Architecture and Computer Engineering,Stuttgart,Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s40820-021-00618-2"},{"issue":"2","key":"ref2","first-page":"186","article-title":"Low-power emerging memristive designs towards secure hardware systems for applications in internet of things","volume-title":"Nano Materials Science","volume":"3","author":"Du","year":"2021"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/adfm.201303365"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CNNA.2012.6331426"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240811"},{"key":"ref7","article-title":"Mixed-mode in-memory computing: Towards high-performance logic processing in a memristive crossbar array","volume-title":"Communications Engineering","author":"Du","year":"2025"},{"key":"ref8","first-page":"1","article-title":"Optimal synthesis of memristive mixed-mode circuits","volume-title":"2025 Design, Automation & Test in Europe Conference (DATE)","author":"Polian"},{"key":"ref9","first-page":"64","article-title":"X-MAGIC: Enhancing PIM using input overwriting capabilities","volume-title":"2020 IFIP\/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)","author":"Peled"},{"key":"ref10","first-page":"225","article-title":"Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic","volume-title":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Ben-Hur"},{"issue":"10","key":"ref11","first-page":"2434","article-title":"SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput","volume":"39","author":"Ben-Hur"},{"key":"ref12","first-page":"105","article-title":"Logic resynthesis of majority-based circuits by top-down decomposition","volume-title":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","author":"Lee"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref14","article-title":"Benchmarks for layout synthesis (mcnc benchmark suite)","volume-title":"Proceedings of the MCNC Workshop on Layout Synthesis","author":"Ko\u017ami\u0144ski"}],"event":{"name":"2026 Design, Automation &amp; Test in Europe Conference (DATE)","location":"Verona, Italy","start":{"date-parts":[[2026,4,20]]},"end":{"date-parts":[[2026,4,22]]}},"container-title":["2026 Design, Automation &amp;amp; Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11539023\/11539024\/11539455.pdf?arnumber=11539455","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:15:15Z","timestamp":1780636515000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11539455\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,20]]},"references-count":14,"URL":"https:\/\/doi.org\/10.23919\/date69613.2026.11539455","relation":{},"subject":[],"published":{"date-parts":[[2026,4,20]]}}}