{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T06:02:06Z","timestamp":1780639326158,"version":"3.54.1"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002635","name":"Inha University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002635","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001321","name":"National Research Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001321","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,20]]},"DOI":"10.23919\/date69613.2026.11539671","type":"proceedings-article","created":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T19:53:10Z","timestamp":1780602790000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["StreamNTT: A High-Throughput, HLS-Based Streaming NTT Accelerator for HBM-Equipped FPGAs"],"prefix":"10.23919","author":[{"given":"Young-Kyu","family":"Choi","sequence":"first","affiliation":[{"name":"Inha University,Department of Computer Engineering,Incheon,South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hyunwoo","family":"Park","sequence":"additional","affiliation":[{"name":"Inha University,Department of Computer Engineering,Incheon,South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei","family":"He","sequence":"additional","affiliation":[{"name":"Rochester Institute of Technology,Department of Electrical and Microelectronic Engineering,Rochester,NY,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sunwoong","family":"Kim","sequence":"additional","affiliation":[{"name":"Rochester Institute of Technology,Department of Electrical and Microelectronic Engineering,Rochester,NY,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3624354.3630585"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3675172"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2020.24203"},{"key":"ref4","article-title":"Introducing NVIDIA cuPQC for GPU-Accelerated Post-Quantum Cryptography","author":"Doroz","year":"2024"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM51124.2021.00032"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-44534-8_19"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3017930"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC54400.2022.9939657"},{"key":"ref9","article-title":"Vitis High-Level Synthesis User Guide (UG1399)","author":"Xilinx","year":"2025"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3184703"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3377366"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM62733.2025.00024"},{"key":"ref13","first-page":"327","article-title":"Post-quantum Key Exchange\u2014A New Hope","volume-title":"USENIX Security Symposium","author":"Alkim"},{"key":"ref14","article-title":"High-performance hardware implementation of lattice-based digital signatures","author":"Beckwith","year":"2022","journal-title":"Cryptology ePrint Archive"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3528416.3530225"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-78713-4_6"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.1145\/3649329.3657379","article-title":"An NTT\/INTT Accelerator with Ultra-High Throughput and Area Efficiency for FHE","volume-title":"Proc. ACM\/IEEE Design Automation Conference (DAC)","author":"Lu"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i2.49-72"},{"key":"ref20","article-title":"RapidStream TAPA Documentation","year":"2025"},{"key":"ref21","volume-title":"AMD Alveo U280 Data Center Accelerator Card: Product Brief","year":"2025"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3312423"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3216544"},{"key":"ref24","article-title":"Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)","year":"2025"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00017"}],"event":{"name":"2026 Design, Automation & Test in Europe Conference (DATE)","location":"Verona, Italy","start":{"date-parts":[[2026,4,20]]},"end":{"date-parts":[[2026,4,22]]}},"container-title":["2026 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11539023\/11539024\/11539671.pdf?arnumber=11539671","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:15:44Z","timestamp":1780636544000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11539671\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,20]]},"references-count":25,"URL":"https:\/\/doi.org\/10.23919\/date69613.2026.11539671","relation":{},"subject":[],"published":{"date-parts":[[2026,4,20]]}}}