{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T06:01:55Z","timestamp":1780639315464,"version":"3.54.1"},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T00:00:00Z","timestamp":1776643200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003392","name":"Natural Science Foundation of Fujian Province","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003392","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,20]]},"DOI":"10.23919\/date69613.2026.11539731","type":"proceedings-article","created":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T19:53:10Z","timestamp":1780602790000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Near-Optimal TDM Ratio Assignment for Die-Level Routing in Multi-FPGA Systems"],"prefix":"10.23919","author":[{"given":"Jiawei","family":"Lin","sequence":"first","affiliation":[{"name":"Fuzhou University,School of Mathematics and Statistics,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Longkun","family":"Guo","sequence":"additional","affiliation":[{"name":"Fuzhou University,School of Mathematics and Statistics,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Weijie","family":"Fang","sequence":"additional","affiliation":[{"name":"Fuzhou University,School of Mathematics and Statistics,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1225959"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3177540.3177542"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISEDA62518.2024.10617705"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3557988.3569711"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00010"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.3.81"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1993.279469"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11132952"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3377551"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942051"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/dac18072.2020.9218667"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1002\/net.3230010302"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218569"},{"key":"ref14","first-page":"176","article-title":"Multi-fpga co-optimization: Hybrid routing and competitive-based time division multiplexing assignment","volume-title":"Proceedings of the 2021 Asia and South Pacific Design Automation Conference, ASPDAC \u201921","author":"Zheng"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2235124"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(88)90066-X"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474255"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3626322"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45586-8_4"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/367766.368168"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1995.242049"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502356"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1137\/0804004"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1287\/moor.21.2.321"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1137\/1013042"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643558"},{"key":"ref27","article-title":"Fpga die-level system routing algorithm design","year":"2023","journal-title":"technical report, S2C"},{"key":"ref28","article-title":"S2C prototyping: FPGA ASIC SoC IP verification, validation, emulation","year":"2024"}],"event":{"name":"2026 Design, Automation & Test in Europe Conference (DATE)","location":"Verona, Italy","start":{"date-parts":[[2026,4,20]]},"end":{"date-parts":[[2026,4,22]]}},"container-title":["2026 Design, Automation & Test in Europe Conference (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11539023\/11539024\/11539731.pdf?arnumber=11539731","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:14:08Z","timestamp":1780636448000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11539731\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,20]]},"references-count":28,"URL":"https:\/\/doi.org\/10.23919\/date69613.2026.11539731","relation":{},"subject":[],"published":{"date-parts":[[2026,4,20]]}}}