{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T00:03:39Z","timestamp":1756771419093,"version":"3.44.0"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.23919\/elinfocom.2019.8706388","type":"proceedings-article","created":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T19:33:11Z","timestamp":1558985591000},"page":"1-2","source":"Crossref","is-referenced-by-count":0,"title":["A Hardware-Friendly Compression Algorithm for Profiling DDR4 Memory Accesses"],"prefix":"10.23919","author":[{"given":"Xuan Truong","family":"Nguyen","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, 08826, Korea"}]},{"given":"Jiwoong","family":"Choi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, 08826, Korea"}]},{"given":"Hyuk-Jae","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, 08826, Korea"}]},{"given":"Hyun","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul, 01811, Korea"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"377","DOI":"10.1145\/2370816.2370870","article-title":"Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches","author":"gennady pekhimenko","year":"2012","journal-title":"In International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.39"},{"journal-title":"Practical Data Compression for Modern Memory Hierarchies","year":"2016","author":"pekhimenko","key":"ref5"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"},{"journal-title":"DDR4 SDRAM Standard","year":"2013","key":"ref1"}],"event":{"name":"2019 International Conference on Electronics, Information, and Communication (ICEIC)","start":{"date-parts":[[2019,1,22]]},"location":"Auckland, New Zealand","end":{"date-parts":[[2019,1,25]]}},"container-title":["2019 International Conference on Electronics, Information, and Communication (ICEIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8698536\/8706336\/08706388.pdf?arnumber=8706388","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T19:14:58Z","timestamp":1756754098000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8706388\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1]]},"references-count":5,"URL":"https:\/\/doi.org\/10.23919\/elinfocom.2019.8706388","relation":{},"subject":[],"published":{"date-parts":[[2019,1]]}}}