{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:09:37Z","timestamp":1767262177947,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.23919\/fmcad.2017.8102261","type":"proceedings-article","created":{"date-parts":[[2017,11,9]],"date-time":"2017-11-09T21:49:00Z","timestamp":1510264140000},"page":"204-211","source":"Crossref","is-referenced-by-count":3,"title":["Estimating worst-case latency of on-chip interconnects with formal simulation"],"prefix":"10.23919","author":[{"given":"Freek","family":"Verbeek","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nike","family":"van Vugt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"214","author":"gotmanov","year":"2011","journal-title":"Verifying Deadlock-Freedom of Communication Fabrics"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2178620"},{"journal-title":"Network on Chip Performance Bound and Tightness","year":"2015","author":"zhao","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2004.1411133"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243841"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NoCS.2013.6558411"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2532871"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0616"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2015.7245728"},{"journal-title":"Network Calculus A Theory of Deterministic Queuing Systems for the Internet","year":"2001","author":"le boudec","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/90.731196"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0149"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2205998"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-12331-3_3"},{"key":"ref9","volume":"2283","author":"nipkow","year":"2002","journal-title":"Isabelle\/HOL A Proof Assistant for Higher-Order Logic"}],"event":{"name":"2017 Formal Methods in Computer-Aided Design (FMCAD)","start":{"date-parts":[[2017,10,2]]},"location":"Vienna","end":{"date-parts":[[2017,10,6]]}},"container-title":["2017 Formal Methods in Computer Aided Design (FMCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8093672\/8102222\/08102261.pdf?arnumber=8102261","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T20:21:06Z","timestamp":1513196466000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8102261\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":16,"URL":"https:\/\/doi.org\/10.23919\/fmcad.2017.8102261","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}