{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:12:31Z","timestamp":1771701151389,"version":"3.50.1"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.23919\/fpl.2017.8056780","type":"proceedings-article","created":{"date-parts":[[2017,10,5]],"date-time":"2017-10-05T16:28:18Z","timestamp":1507220898000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["The Monte Carlo PUF"],"prefix":"10.23919","author":[{"given":"Vladimir","family":"Rozic","sequence":"first","affiliation":[]},{"given":"Bohan","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Jo","family":"Vliegen","sequence":"additional","affiliation":[]},{"given":"Nele","family":"Mentens","sequence":"additional","affiliation":[]},{"given":"Ingrid","family":"Verbauwhede","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681648"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1145\/1278480.1278484","article-title":"physical unclonable functions for device authentication and secret key generation","author":"suh","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2165540"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15031-9_25"},{"key":"ref14","year":"2010","journal-title":"Spartan-6 FPGA Configuration Logic Block User Guide Xilinx Inc"},{"key":"ref15","year":"2016","journal-title":"Cyclone II Device Handbook Altera Corporation"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419927"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577307"},{"key":"ref18","year":"2012","journal-title":"Spartan-6 FPGA Configuration Logic Block User Guide Xilinx Inc"},{"key":"ref19","year":"2016","journal-title":"Series FPGAs Configuration Logic Block User Guide Xilinx Inc"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1007\/978-3-540-74735-2_5","article-title":"FPGA Intrinsic PUFs and Their Use for IP Protection","author":"guajardo","year":"2007","journal-title":"9th International Workshop Cryptographic Hardware and Embedded Systems 2007"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/586110.586132"},{"key":"ref6","article-title":"Intrinsic PUFs from Flip-flops on Reconfigurable Devices","author":"maes","year":"2008","journal-title":"Workshop on Information and System Security"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373466"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2008.4559053"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2012.6224311"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"2026","DOI":"10.1126\/science.1074376","article-title":"Physical One-Way Functions","volume":"297","author":"pappu","year":"2002","journal-title":"Science"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-013-5430-8"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1200","DOI":"10.1109\/TVLSI.2005.859470","article-title":"Extracting secret keys from integrated circuits","volume":"13","author":"lim","year":"2005","journal-title":"IEEE Trans VLSI Syst"}],"event":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","location":"Ghent, Belgium","start":{"date-parts":[[2017,9,4]]},"end":{"date-parts":[[2017,9,8]]}},"container-title":["2017 27th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8049195\/8056751\/08056780.pdf?arnumber=8056780","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,4]],"date-time":"2019-10-04T05:00:04Z","timestamp":1570165204000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8056780\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/fpl.2017.8056780","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}