{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T15:45:18Z","timestamp":1762875918860},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.23919\/fpl.2017.8056810","type":"proceedings-article","created":{"date-parts":[[2017,10,5]],"date-time":"2017-10-05T16:28:18Z","timestamp":1507220898000},"page":"1-8","source":"Crossref","is-referenced-by-count":9,"title":["Tile size selection for optimized memory reuse in high-level synthesis"],"prefix":"10.23919","author":[{"given":"Junyi","family":"Liu","sequence":"first","affiliation":[]},{"given":"John","family":"Wickerson","sequence":"additional","affiliation":[]},{"given":"George A.","family":"Constantinides","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2555292"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021736"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.167"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.18"},{"journal-title":"Theory of Linear and Integer Programming","year":"1998","author":"schrijver","key":"ref15"},{"journal-title":"Integer Programming and Network Flows","year":"1969","author":"hu","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511804441"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CACSD.2004.1393890"},{"key":"ref19","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Advances in Neural Information Processing Systems 25 Curran Associates Inc"},{"journal-title":"Intel FPGA SDK for OpenCL Programming Guide","article-title":"Intel","year":"0","key":"ref4"},{"journal-title":"Xilinx","article-title":"Vivado Design Suite User Guide: High-Level Synthesis","year":"0","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1379022.1375595"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1033"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435273"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554780"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691121"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/207110.207162"}],"event":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2017,9,4]]},"location":"Ghent, Belgium","end":{"date-parts":[[2017,9,8]]}},"container-title":["2017 27th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8049195\/8056751\/08056810.pdf?arnumber=8056810","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,27]],"date-time":"2017-10-27T17:32:11Z","timestamp":1509125531000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8056810\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/fpl.2017.8056810","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}