{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T03:16:02Z","timestamp":1730344562781,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,9,28]]},"DOI":"10.23919\/mipro48935.2020.9245364","type":"proceedings-article","created":{"date-parts":[[2020,11,6]],"date-time":"2020-11-06T21:51:34Z","timestamp":1604699494000},"page":"118-122","source":"Crossref","is-referenced-by-count":0,"title":["Sequential Register Renaming"],"prefix":"10.23919","author":[{"given":"Dejan","family":"Spasov","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050009"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2062545"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2270001"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264119"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974714"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1147\/rd.111.0025","article-title":"An efficient algorithm for exploiting multiple arithmetic units","volume":"11","author":"tomasulo","year":"1967","journal-title":"IBM Journal of Research and Development"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.491.0167"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2011","author":"weste","key":"ref6"},{"key":"ref5","article-title":"The Microarchitecture of the Pentium® 4 Processor","author":"hinton","year":"2001","journal-title":"Intel Technology Journal"},{"key":"ref8","first-page":"449452","article-title":"Tapered transmission gate chains for improved carry propagation","author":"andreev","year":"2002","journal-title":"The 2002 45th Midwest Symposium on Circuits and Systems"},{"journal-title":"Digital Integrated Circuits","year":"2003","author":"rabaey","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.476078"},{"key":"ref9","article-title":"Power-aware Register Renaming","author":"moshovos","year":"2002","journal-title":"Technical Report Computer Engineering Croup University of Toronto"}],"event":{"name":"2020 43rd International Convention on Information, Communication and Electronic Technology (MIPRO)","start":{"date-parts":[[2020,9,28]]},"location":"Opatija, Croatia","end":{"date-parts":[[2020,10,2]]}},"container-title":["2020 43rd International Convention on Information, Communication and Electronic Technology (MIPRO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9245088\/9245075\/09245364.pdf?arnumber=9245364","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,1,13]],"date-time":"2021-01-13T05:10:06Z","timestamp":1610514606000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9245364\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,28]]},"references-count":14,"URL":"https:\/\/doi.org\/10.23919\/mipro48935.2020.9245364","relation":{},"subject":[],"published":{"date-parts":[[2020,9,28]]}}}