{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T03:12:46Z","timestamp":1730344366944,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.23919\/mixdes.2018.8436679","type":"proceedings-article","created":{"date-parts":[[2018,8,17]],"date-time":"2018-08-17T20:14:20Z","timestamp":1534536860000},"page":"275-279","source":"Crossref","is-referenced-by-count":1,"title":["Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology"],"prefix":"10.23919","author":[{"given":"Bartosz","family":"Dec","sequence":"first","affiliation":[]},{"given":"Andrzej","family":"Pfitzner","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2015.7285054"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2009.5166288"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117782"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2016.7529756"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2577629"},{"key":"ref15","article-title":"N-channel Junction-less Vertical Slit Field-Effect Transistor (VeSFET): Fabrication-based Feasibility Assessment","author":"chen","year":"0","journal-title":"2012 Int Conf on Solid-State and Integrated Circuit (ICSIC 2012))"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2176309"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ULIS.2017.7962604"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/MIXDES.2017.8005169"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/INDICON.2015.7443732"},{"key":"ref4","first-page":"151","article-title":"Vertical-Slit Field-Effect Transistor (VeSFET)-Design Space Exploration and DC Model","author":"pfitzner","year":"2011","journal-title":"Proc 18th Int Conf MIXDES"},{"key":"ref3","first-page":"145","article-title":"Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration","author":"maly","year":"2011","journal-title":"Proc 18th Int Conf MIXDES"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187522"},{"key":"ref5","first-page":"121","article-title":"A Compact Model of VeSFET Capacitances","author":"kasprowicz","year":"2011","journal-title":"Proc 18th Int Conf MIXDES"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2014.6872210"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2013.6549816"},{"key":"ref2","article-title":"Complementary Vertical Slit Field Effect Transistors","author":"maly","year":"2008","journal-title":"Tech report No CSSI 08-02"},{"key":"ref9","first-page":"869","article-title":"Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips","volume":"33","author":"qiu","year":"2014","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"journal-title":"Integrated Circuit Device System and Method of Fabrication","year":"2009","author":"maly","key":"ref1"},{"key":"ref20","first-page":"420","article-title":"DC Characteristics of Junction Vertical Slit Field-Effect Transistor (JVeSFET)","author":"pfitzner","year":"2009","journal-title":"Proc 16th Int Conf MIXDES"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2014.6872214"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2014.6872217"},{"journal-title":"Synopsys","article-title":"Sentaurus Device User Guide","year":"0","key":"ref24"},{"key":"ref23","article-title":"Bipolar transistor in VESTIC technology: prototype","author":"mierzwinski","year":"2016","journal-title":"Proc SPIE 10175 Electron Technology Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SMICND.2013.6688073"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NVMT.1996.534669"}],"event":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","start":{"date-parts":[[2018,6,21]]},"location":"Gdynia, Poland","end":{"date-parts":[[2018,6,23]]}},"container-title":["2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8422065\/8436585\/08436679.pdf?arnumber=8436679","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T22:18:09Z","timestamp":1598221089000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8436679\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":26,"URL":"https:\/\/doi.org\/10.23919\/mixdes.2018.8436679","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}