{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T03:55:54Z","timestamp":1754020554695,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.23919\/mixdes.2018.8436851","type":"proceedings-article","created":{"date-parts":[[2018,8,17]],"date-time":"2018-08-17T16:14:20Z","timestamp":1534522460000},"page":"154-159","source":"Crossref","is-referenced-by-count":1,"title":["High-Speed 32*32 bit Multiplier in 0.18um CMOS Process"],"prefix":"10.23919","author":[{"given":"Ebrahim","family":"Hosseini","sequence":"first","affiliation":[{"name":"Microelectronic Research Laboratory, Urmia University, Urmia, Iran"}]},{"given":"Morteza","family":"Mousazadeh","sequence":"additional","affiliation":[{"name":"Microelectronic Research Laboratory, Urmia University, Urmia, Iran"}]},{"given":"Abdollah","family":"Amini","sequence":"additional","affiliation":[{"name":"Urumi Graduate Institute(UGI), Urmia, Iran"}]}],"member":"263","reference":[{"key":"ref10","first-page":"240","article-title":"Basic VLSI Design","author":"pucknell","year":"1994","journal-title":"Prentice Hall"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/263272.263337"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1956.5219801"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1961.287779"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/pi-b-2.1960.0171"},{"key":"ref15","first-page":"691","article-title":"Skip Techniques for High Speed Carry in Binary Arithemtic Units","volume":"ec 10","author":"lehman","year":"1962","journal-title":"IRE Trans Ma Electron"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IRETELC.1962.5407919"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009159"},{"key":"ref18","first-page":"1098","article-title":"A Novel Design of a 6-GHz 8 &#x00D7; 8-bit Pipelined Multiplier","volume":"5","author":"khatibzadeh","year":"2005","journal-title":"The International Database Engineering and Applications Symposium"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2012.0221"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2010.10"},{"key":"ref3","first-page":"1","article-title":"Design of High-speed Modified Booth Multiplier Operating at GHz Ranges","volume":"61","author":"kim","year":"2010","journal-title":"World Academy of Science Engineering and Technology"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.156"},{"key":"ref5","first-page":"57","article-title":"A 64&#x00D7;64-bit Modified Booth Multiplier Utilizing Multiplexer-Select Booth Encoder","volume":"1","author":"wu","year":"2005","journal-title":"ASICON 6th Int Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494026"},{"key":"ref7","first-page":"85","article-title":"A well-structured modified Booth multiplier design","author":"wang","year":"2008","journal-title":"Proc of IEEE VLSI-DAT"},{"key":"ref2","first-page":"121","article-title":"A 3. 3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder","volume":"5","author":"chow","year":"2003","journal-title":"Proc IEEE ISCAS"},{"key":"ref1","first-page":"457","article-title":"A 3. 3V 1GHz high speed pipelined Booth multiplier","volume":"1","author":"chow","year":"2002","journal-title":"Proc of IEEE ISCAS"},{"key":"ref9","first-page":"1","article-title":"A l. 6GHz 16&#x00D7;16-bit Low-Latency Pipelined Booth Multiplier","author":"ghasemizadeh","year":"2011","journal-title":"19th Iranian Conference on Electrical Engineering (ICEE)"}],"event":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","start":{"date-parts":[[2018,6,21]]},"location":"Gdynia, Poland","end":{"date-parts":[[2018,6,23]]}},"container-title":["2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8422065\/8436585\/08436851.pdf?arnumber=8436851","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,13]],"date-time":"2023-01-13T17:25:48Z","timestamp":1673630748000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8436851\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/mixdes.2018.8436851","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}