{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T02:11:32Z","timestamp":1725502292062},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.23919\/mixdes.2018.8436860","type":"proceedings-article","created":{"date-parts":[[2018,8,17]],"date-time":"2018-08-17T16:14:20Z","timestamp":1534522460000},"page":"218-222","source":"Crossref","is-referenced-by-count":0,"title":["Using Verilog-to-Routing Framework for Coarse-Grained Reconfigurable Architecture Routing"],"prefix":"10.23919","author":[{"given":"Zbigniew","family":"Mudza","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046194"},{"key":"ref3","article-title":"Instructionless General Purpose Coarse-GrainedReconfigurable Processor Performance in Encryption","author":"mudza","year":"2017","journal-title":"Mixed Design of Integrated Circuits and Systems (MIXDES)"},{"key":"ref6","article-title":"A Fully Pipelined and Dynamically Composable Architecture of CGR","author":"cong","year":"2014","journal-title":"Field-Programmable Custom Computing Machines Annual IEEE Symposium on"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2010.5541009"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1109\/ISVLSI.2016.54","article-title":"A Scalable Design Approach to Efficiently Map Applications on CGRAs","author":"das","year":"2016","journal-title":"2016 IEEE Computer Society Annual Symposium on VLSI IEEE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2016.7818353"},{"key":"ref2","article-title":"Instructionless processor architecture using dynamically reconfigurable logic","author":"kielbik","year":"2010","journal-title":"Mixed Design of Integrated Circuits and Systems (MIXDES)"},{"key":"ref9","article-title":"Efficient Mapping of CDFG onto Coarse-Grained Reconfigurable Array Architectures","author":"das","year":"2017","journal-title":"Asia South Pacific Design Automation Conf (ASP-DAC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"}],"event":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","start":{"date-parts":[[2018,6,21]]},"location":"Gdynia, Poland","end":{"date-parts":[[2018,6,23]]}},"container-title":["2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8422065\/8436585\/08436860.pdf?arnumber=8436860","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T21:13:53Z","timestamp":1598217233000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8436860\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":9,"URL":"https:\/\/doi.org\/10.23919\/mixdes.2018.8436860","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}