{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,18]],"date-time":"2025-04-18T05:11:40Z","timestamp":1744953100052,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.23919\/mixdes.2018.8443590","type":"proceedings-article","created":{"date-parts":[[2018,8,23]],"date-time":"2018-08-23T22:04:04Z","timestamp":1535061844000},"page":"109-115","source":"Crossref","is-referenced-by-count":4,"title":["A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18\u03bcm Technology"],"prefix":"10.23919","author":[{"given":"Faeze","family":"Noruzpur","sequence":"first","affiliation":[]},{"given":"Sina","family":"Mahdavi","sequence":"additional","affiliation":[]},{"given":"Maryam","family":"Poreh","sequence":"additional","affiliation":[]},{"given":"Shima Tayyeb","family":"Ghasemi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"A Low Power 1 5GHz Clock and Data Recovery Circuit in 0 35um CMOS Process","year":"2011","author":"mehraban","key":"ref10"},{"journal-title":"Design and Implementation of a 1 5GHz Wideband Fractional-N PLL Frequency Synthesizer in 0 35?m Process","year":"2011","author":"azizian","key":"ref11"},{"journal-title":"A Dual-Loop frequency synthesizer","year":"2006","author":"karsani","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168688"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2011.6126710"},{"journal-title":"Design and analysis of efficient Phase Locked Loop for fast phase and frequency acquisition","year":"2011","author":"panda","key":"ref15"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"910","DOI":"10.1109\/4.924853","article-title":"A 1. 25-GHz 0. 35-_m Monolithic CMOS PLL Based on a Multiphase Ring Oscillator","volume":"36","author":"sun","year":"2001","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1151","DOI":"10.1109\/JSSC.2013.2252515","article-title":"A 90-nm CMOS 5-GHz ring-oscillator PLL with delay-discriminator-based active phase-noise cancellation","volume":"48","author":"seungkee","year":"2013","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2012.6403127"},{"journal-title":"A multi-band phase-locked loop frequency synthesizer","year":"1999","author":"palermo","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1980.1094619"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/30\/8\/085011"},{"journal-title":"Design and fabrication of a self biased PLL for frequency range of 50MHz-200MHz and RMS jitter less than 75ps in 0 5um CMOS process","year":"2014","author":"haseli","key":"ref6"},{"journal-title":"Design of a Phase Locked Loop based clocking circuit for high speed serial link applications","year":"2014","author":"ratan","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2209810"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2476295"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2537823"},{"key":"ref1","first-page":"1416","article-title":"A Study on Design of PLL for Low Phase-Noise Characteristics","author":"hobara","year":"2012","journal-title":"Proceedings of SICE Annual Conference SICE2011"},{"key":"ref9","first-page":"31","article-title":"A 40GHz PLL with-92. 5dBc\/Hz In-Band Phase Noise and 104fs-RMS-Jitter","author":"chen","year":"2017","journal-title":"IEEE Radio Frequency Integrated Circuits Symposium RFIC"},{"key":"ref20","first-page":"238","article-title":"Time-varying, frequency domain modeling and analysis of phase-locked loops with sampling phase-frequency detectors","author":"vanassche","year":"2003","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"journal-title":"Low-power low-jitter on-chip clock generation","year":"2003","author":"mansuri","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.852934"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.834516"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.01.003"}],"event":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","start":{"date-parts":[[2018,6,21]]},"location":"Gdynia, Poland","end":{"date-parts":[[2018,6,23]]}},"container-title":["2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8422065\/8436585\/08443590.pdf?arnumber=8443590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T15:52:51Z","timestamp":1643212371000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8443590\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":24,"URL":"https:\/\/doi.org\/10.23919\/mixdes.2018.8443590","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}