{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:43:29Z","timestamp":1725810209586},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,6,27]],"date-time":"2024-06-27T00:00:00Z","timestamp":1719446400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,6,27]],"date-time":"2024-06-27T00:00:00Z","timestamp":1719446400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,6,27]]},"DOI":"10.23919\/mixdes62605.2024.10614028","type":"proceedings-article","created":{"date-parts":[[2024,8,2]],"date-time":"2024-08-02T17:20:23Z","timestamp":1722619223000},"page":"193-198","source":"Crossref","is-referenced-by-count":0,"title":["Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology"],"prefix":"10.23919","author":[{"given":"Bartosz","family":"Dec","sequence":"first","affiliation":[{"name":"Institute of Microelectronics and Optoelectronics, Warsaw University of Technology,Warsaw,Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrzej","family":"Pfitzner","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics and Optoelectronics, Warsaw University of Technology,Warsaw,Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"issue":"US9640653B2","key":"ref1","article-title":"Integrated circuit device, system, and method of fabrication","author":"Maly","year":"2012","journal-title":"UNITED STATES PATENT"},{"key":"ref2","first-page":"145","article-title":"Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration","volume-title":"Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011","author":"Maly","year":"2011"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ULIS.2017.7962604"},{"key":"ref4","first-page":"96","article-title":"A compact model of VES-BJT device","volume-title":"Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013","author":"Kuzmicz","year":"2013"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2014.6872214"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/MIXDES.2018.8436679"},{"key":"ref7","article-title":"Vertical-Slit Field-Effect Transistor (VeSFET) - design space exploration and DC model","volume-title":"Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011","author":"Pfitzner","year":"2011"},{"key":"ref8","article-title":"VESTIC: A New IC Manufacturing Paradigm: Present Status and Future Plans","volume-title":"29th Int. Conf. MIXDES2022, Special Session presentation","author":"Pfitzner","year":"2022"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/MIXDES.2018.8436648"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/5.622505"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2007.378943"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2002.1035411"},{"key":"ref13","article-title":"Feasibility studies of EAROM non-volatile memory in VeSTIC technology based on Charge Trapping effect","volume-title":"Warsaw University of Technology","author":"Dec","year":"2019"},{"key":"ref14","first-page":"192","article-title":"Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory","volume-title":"2009 Symposium on VLSI Technology","author":"Jang","year":"2009"}],"event":{"name":"2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","start":{"date-parts":[[2024,6,27]]},"location":"Gdansk, Poland","end":{"date-parts":[[2024,6,28]]}},"container-title":["2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10613861\/10613931\/10614028.pdf?arnumber=10614028","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,3]],"date-time":"2024-08-03T05:31:41Z","timestamp":1722663101000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10614028\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,27]]},"references-count":14,"URL":"https:\/\/doi.org\/10.23919\/mixdes62605.2024.10614028","relation":{},"subject":[],"published":{"date-parts":[[2024,6,27]]}}}