{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:28:58Z","timestamp":1781195338359,"version":"3.54.1"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.23919\/vlsic.2019.8777934","type":"proceedings-article","created":{"date-parts":[[2019,7,29]],"date-time":"2019-07-29T23:44:52Z","timestamp":1564443892000},"page":"C238-C239","source":"Crossref","is-referenced-by-count":6,"title":["A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array"],"prefix":"10.23919","author":[{"given":"Sudhir","family":"Satpathy","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vikram","family":"Suresh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Raghavan","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vinodh","family":"Gopal","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"James","family":"Guilford","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mark","family":"Anders","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Himanshu","family":"Kaul","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Amit","family":"Agarwal","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Steven","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ram","family":"Krishnamurthy","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sanu","family":"Mathew","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","author":"zhu","year":"2013","journal-title":"ISCAS"},{"key":"ref3","author":"kim","year":"2015","journal-title":"ISSCC"},{"key":"ref6","author":"reyenders","year":"2014","journal-title":"ISSCC"},{"key":"ref5","author":"deguchi","year":"2017","journal-title":"VLSI Circuits Symp"},{"key":"ref8","author":"zaretxky","year":"2009","journal-title":"ISCAS"},{"key":"ref7","author":"okano","year":"2016","journal-title":"FPGA4GPC"},{"key":"ref2","author":"satpathy","year":"2018","journal-title":"ESSCIRC"},{"key":"ref1","author":"martin","year":"2013","journal-title":"ICCAD"}],"event":{"name":"2019 Symposium on VLSI Circuits","location":"Kyoto, Japan","start":{"date-parts":[[2019,6,9]]},"end":{"date-parts":[[2019,6,14]]}},"container-title":["2019 Symposium on VLSI Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8766307\/8777931\/08777934.pdf?arnumber=8777934","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,22]],"date-time":"2019-08-22T17:20:23Z","timestamp":1566494423000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8777934\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6]]},"references-count":8,"URL":"https:\/\/doi.org\/10.23919\/vlsic.2019.8777934","relation":{},"subject":[],"published":{"date-parts":[[2019,6]]}}}