{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T07:24:30Z","timestamp":1769844270055,"version":"3.49.0"},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.23919\/vlsic.2019.8778041","type":"proceedings-article","created":{"date-parts":[[2019,7,29]],"date-time":"2019-07-29T19:44:52Z","timestamp":1564429492000},"page":"C234-C235","source":"Crossref","is-referenced-by-count":3,"title":["A 4900\u00d7m<sup>2<\/sup> 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition"],"prefix":"10.23919","author":[{"given":"Raghavan","family":"Kumar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vikram","family":"Suresh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Monodeep","family":"Kar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudhir","family":"Satpathy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Anders","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Himanshu","family":"Kaul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Agarwal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gregory","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ram","family":"Krishnamurthy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanu","family":"Mathew","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"246c","author":"lu","year":"2015","journal-title":"VLSI Circuits Symposium"},{"key":"ref3","first-page":"446","author":"canright","year":"2008","journal-title":"Proc of ACNS"},{"key":"ref6","first-page":"142","author":"kar","year":"2017","journal-title":"ISSCC"},{"key":"ref5","first-page":"64","author":"tokunaga","year":"2009","journal-title":"ISSCC"},{"key":"ref2","first-page":"274","author":"doulcier-verdier","year":"2011","journal-title":"ISSCC"},{"key":"ref1","first-page":"126","author":"yang","year":"2018","journal-title":"ISSCC"}],"event":{"name":"2019 Symposium on VLSI Circuits","location":"Kyoto, Japan","start":{"date-parts":[[2019,6,9]]},"end":{"date-parts":[[2019,6,14]]}},"container-title":["2019 Symposium on VLSI Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8766307\/8777931\/08778041.pdf?arnumber=8778041","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,22]],"date-time":"2019-08-22T13:20:35Z","timestamp":1566480035000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8778041\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6]]},"references-count":6,"URL":"https:\/\/doi.org\/10.23919\/vlsic.2019.8778041","relation":{},"subject":[],"published":{"date-parts":[[2019,6]]}}}