{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:12:43Z","timestamp":1725783163502},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.23919\/vlsic.2019.8778147","type":"proceedings-article","created":{"date-parts":[[2019,7,29]],"date-time":"2019-07-29T19:44:52Z","timestamp":1564429492000},"page":"C150-C151","source":"Crossref","is-referenced-by-count":2,"title":["A 7.3 M Output Non-Zeros\/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm"],"prefix":"10.23919","author":[{"given":"Subhankar","family":"Pal","sequence":"first","affiliation":[]},{"given":"Dong-hyeon","family":"Park","sequence":"additional","affiliation":[]},{"given":"Siying","family":"Feng","sequence":"additional","affiliation":[]},{"given":"Paul","family":"Gao","sequence":"additional","affiliation":[]},{"given":"Jielun","family":"Tan","sequence":"additional","affiliation":[]},{"given":"Austin","family":"Rovinski","sequence":"additional","affiliation":[]},{"given":"Shaolin","family":"Xie","sequence":"additional","affiliation":[]},{"given":"Chun","family":"Zhao","sequence":"additional","affiliation":[]},{"given":"Aporva","family":"Amarnath","sequence":"additional","affiliation":[]},{"given":"Timothy","family":"Wesley","sequence":"additional","affiliation":[]},{"given":"Jonathan","family":"Beaumont","sequence":"additional","affiliation":[]},{"given":"Kuan-Yu","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Chaitali","family":"Chakrabarti","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Taylor","sequence":"additional","affiliation":[]},{"given":"Trevor","family":"Mudge","sequence":"additional","affiliation":[]},{"given":"David","family":"Blaauw","sequence":"additional","affiliation":[]},{"given":"Hun-Seok","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Ronald","family":"Dreslinski","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"478","author":"satpathy","year":"2012","journal-title":"ISSCC"},{"key":"ref3","first-page":"39","author":"anders","year":"2018","journal-title":"ISSCC"},{"key":"ref5","first-page":"39","author":"khorasani","year":"2015","journal-title":"PACT"},{"key":"ref2","first-page":"1","author":"dorrance","year":"2016","journal-title":"VLSI"},{"key":"ref1","first-page":"724","author":"pal","year":"2018","journal-title":"HPCA"}],"event":{"name":"2019 Symposium on VLSI Circuits","start":{"date-parts":[[2019,6,9]]},"location":"Kyoto, Japan","end":{"date-parts":[[2019,6,14]]}},"container-title":["2019 Symposium on VLSI Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8766307\/8777931\/08778147.pdf?arnumber=8778147","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,22]],"date-time":"2019-08-22T13:20:32Z","timestamp":1566480032000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8778147\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6]]},"references-count":5,"URL":"https:\/\/doi.org\/10.23919\/vlsic.2019.8778147","relation":{},"subject":[],"published":{"date-parts":[[2019,6]]}}}