{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T10:36:38Z","timestamp":1769855798192,"version":"3.49.0"},"reference-count":2,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,6,13]]},"DOI":"10.23919\/vlsicircuits52068.2021.9492467","type":"proceedings-article","created":{"date-parts":[[2021,7,28]],"date-time":"2021-07-28T20:33:42Z","timestamp":1627504422000},"page":"1-2","source":"Crossref","is-referenced-by-count":7,"title":["A 1.24pJ\/b 112Gb\/s (870Gbps\/mm) Transceiver for In-package Links in 7nm FinFET"],"prefix":"10.23919","author":[{"given":"Chi Fung","family":"Poon","sequence":"first","affiliation":[]},{"given":"Wenfeng","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Junho","family":"Cho","sequence":"additional","affiliation":[]},{"given":"Shaojun","family":"Ma","sequence":"additional","affiliation":[]},{"given":"Yipeng","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Ying","family":"Cao","sequence":"additional","affiliation":[]},{"given":"Asma","family":"Laraba","sequence":"additional","affiliation":[]},{"given":"Eugene","family":"Ho","sequence":"additional","affiliation":[]},{"given":"Winson","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Daniel","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Kee Hian","family":"Tan","sequence":"additional","affiliation":[]},{"given":"Parag","family":"Upadhyaya","sequence":"additional","affiliation":[]},{"given":"Yohan","family":"Frans","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref2","first-page":"7","article-title":"A 112Gb\/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET","volume":"56","author":"im","year":"2021","journal-title":"JSSC"},{"key":"ref1","year":"0","journal-title":"Extreme Short Reach Interface"}],"event":{"name":"2021 Symposium on VLSI Circuits","location":"Kyoto, Japan","start":{"date-parts":[[2021,6,13]]},"end":{"date-parts":[[2021,6,19]]}},"container-title":["2021 Symposium on VLSI Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9492225\/9492226\/09492467.pdf?arnumber=9492467","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,6]],"date-time":"2021-12-06T21:18:07Z","timestamp":1638825487000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9492467\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,13]]},"references-count":2,"URL":"https:\/\/doi.org\/10.23919\/vlsicircuits52068.2021.9492467","relation":{},"subject":[],"published":{"date-parts":[[2021,6,13]]}}}