{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:47:08Z","timestamp":1730342828199,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8714809","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T17:29:07Z","timestamp":1558027747000},"page":"1637-1642","source":"Crossref","is-referenced-by-count":7,"title":["A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices"],"prefix":"10.23919","author":[{"given":"Levent","family":"Aksoy","sequence":"first","affiliation":[]},{"given":"Mustafa","family":"Altun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.05.004"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2018.08.002"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"ref13","first-page":"399","article-title":"Predicting learnt clauses quality in modern sat solver","author":"audemard","year":"2009","journal-title":"IJCAI"},{"key":"ref14","article-title":"Logic synthesis and optimization benchmarks user guide: Version 3.0","author":"yang","year":"1991","journal-title":"MCNC Tech Rep"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.08.004"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.170"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2661632"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715123"},{"key":"ref8","first-page":"1","article-title":"Synthesis of switching lattices of dimensional-reducible boolean functions","author":"bernasconi","year":"2016","journal-title":"VLSI-SoC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.108614"},{"key":"ref2","first-page":"997","article-title":"Nanowire crossbar logic and standard cell-based integration","volume":"17","author":"dong","year":"2009","journal-title":"IEEE TVLSI"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1084748.1084750"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2016.75"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2019,3,25]]},"location":"Florence, Italy","end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08714809.pdf?arnumber=8714809","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,3]],"date-time":"2019-06-03T19:50:34Z","timestamp":1559591434000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8714809\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8714809","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}